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Advisory September 2001
Ambassador (R) T8110 Version History
Introduction
The purpose of this advisory is to provide information on the different versions of the Ambassador T8110.
T8110 Version 1
Models of the T8110 V1 had two device issues. The two device issues only affect the microprocessor interface and packet switching capabilities. The T8110 V1 can function as a 4096 connection standard telephony switch when using the PCI interface. Issue 1: Microprocessor interface: The RDY(DTACKn) signal can oscillate if the microprocessor device driving the microprocessor interface does not relinquish its RDn (or WRn) signal within one 65 MHz clock cycle after the reassertion of RDY (Intel (R) mode) or deassertion of DTACKn (Motorola (R) mode). The processor or board-level component driving the microprocessor port must deassert RDn or WRn immediately (within 15 ns) upon reassertion of RDY. Packet switch malfunction: The T8110 does not disable its upper byte lanes on the descriptor table update, resulting in an over-write of descriptor table data. The descriptor table update occurs as the last phase of a PCI Master PUSH & PULL cycle. This results in virtual channel connection malfunctions. TDM switching is unaffected. A systemic workaround for the user is to keep a shadow table for the UOR portion of the descriptor table.
Workaround: Issue 2:
Workaround:
T8110 version 1 models can be identified by the markings on the device or by reading the version ID register. If the last line of the device markings is a 7 digit number followed by no version number, then the device is a version 1. Reading the version ID register 0x00128 will read back a value of 01h, indicating the device is version 1. Samples of version 1 are no longer available (version 2 samples are now available).
T8110 Version 2
Models of the T8110 V2 have one device issue. The device issue only affects the packet switching capabilities. The T8110 V2 can function as a 4096 connection standard telephony switch when using either PCI or microprocessor interface. Issue 1 (from version 1): Fixed. The microprocessor interface issue has been resolved. Issue 2 (from version 1): Will be fixed in version 3. T8110 version 2 models can be identified by the markings on the device or by reading the version ID register. If the last line of the device markings is a 7 digit number followed by V2, then the device is a version 2. Reading the version ID register 0x00128 will read back a value of 02h, indicating the device is a version 2. Samples of version 2 are currently available. For additional information, contact your local FAE (field application engineer), or call 1-800-372-2447.
Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc.
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved
September 2001 AY01-038CTI (Replaces AY01-021CTI and must accompany DS00-434CTI)
Data Sheet May 2001
Ambassador (R) T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
1 Introduction
The T8110 is Agere Systems Inc.'s newest addition to the Ambassador series of computer telephony integrated circuits. This device not only has the capabilities of previous members of the Ambassador series but also extends them by providing a flexible interface for switching packet payloads between a local PCI bus and the H.100/H.110 buses. Packets may also be switched between the local PCI bus and local TDM streams. This part is intended to work with a coprocessor for providing header, framing, and checksum generation. Since the T8110 operates purely on payloads, multiple protocols such as IP, ATM, and A-Bis can therefore be supported simultaneously. To reduce system integration costs, support for non-PCI devices is provided through a minibridge.
n T1/E1 rate adaptation n Two clock-fallback modes n Stratum 4/4E and AT&T 62411 MTIE compliant n Incorporates 38 H.100 and 34 H.110 termination resistors n Subrate switching of 4 bits, 2 bits, or 1 bit n Backward compatible to all T810x devices n JTAG/boundary-scan testing support n BSDL files available n Assists H.110 hot swap n Single 3.3 V supply with 5 V tolerant inputs and TTL compatible outputs n 272 PBGA package n Evaluation boards available, PCI and CompactPCI Hot Swap
1.1 Features
n 4,096-connection unified switch
FRAMERS
n Full H.100/H.110 support (32 data lines, all clock modes) n 32 local I/O lines (2, 4, 8, or 16 Mbits/s) n PCI interface: combined master/slave with burst n Microprocessor interface: Motorola*/Intel modes n Minibridge with programmable chip selects n Interrupt controller with external inputs n Eight independent general-purpose I/O lines n Eight independently programmed framing signals n Four local clocks
TRUNKS
STREAMS AGERE T8110 PCI BRIDGE I/F COPROCESSOR PCI
& CLOCKS
STREAMS
n Packet payload engine supports up to 512 virtual channels
H.100 BUS
ETHERNET 10/100 MAC/PHY PCI
LOCAL PCI BUS
PCI
MEMORY
PCI-PCI BRIDGE
HOST PCI BUS
5-8921F
Figure 1. Basic Application of the T8110 as a CT Switch and CT-IP Payload Processor
* Motorola is a registered trademark of Motorola, Inc. Intel is a registered trademark of Intel Corporation. CompactPCI is a registered trademark of the PCI Industrial Computer Manufacturers Group.
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
Table of Contents
Contents Page
1 Introduction ............................................................................................................................................................1 1.1 Features .......................................................................................................................................................... 1 2 Pin Description ...................................................................................................................................................... 8 2.1 Interface Signals ............................................................................................................................................. 8 2.2 T8110 Pinout Information ............................................................................................................................. 11 2.3 Special Buffer Requirements ........................................................................................................................ 18 2.3.1 H1x0 Bus Signal Internal Pull-Up/Pull-Down ................................................................................... 18 2.3.2 Local Bus Signal Internal Pull-Up .................................................................................................... 18 3 Main Architectural Features ................................................................................................................................ 19 3.1 T8110 Architecture .......................................................................................................................................19 4 PCI Interface ....................................................................................................................................................... 22 4.1 Target ........................................................................................................................................................... 22 4.1.1 PCI Interface Registers ....................................................................................................................23 4.1.2 Register Space Target Access ........................................................................................................29 4.1.3 Connection Memory Space Target Access .....................................................................................29 4.1.4 Data Memory Space Target Access ................................................................................................ 29 4.1.4.1 Posted Write Transaction .................................................................................................... 29 4.1.4.2 Delayed Read Transaction .................................................................................................. 30 4.1.5 Virtual Channel Memory Space Target Access ............................................................................... 30 4.1.5.1 Posted Write Transaction .................................................................................................... 30 4.1.5.2 Delayed Read Transaction .................................................................................................. 30 4.1.6 Minibridge Space Target Access ..................................................................................................... 30 4.1.6.1 Posted Write Transaction .................................................................................................... 31 4.1.6.2 Delayed Read Transaction .................................................................................................. 31 4.2 Initiator ..........................................................................................................................................................31 4.2.1 PUSH Operation (Upstream Transaction) ....................................................................................... 31 4.2.2 PULL Operation (Downstream Transaction) .................................................................................... 32 4.3 Configuration Space/EEPROM Interface ...................................................................................................... 34 4.3.1 Loadable PCI Configuration Space Via EEPROM ........................................................................... 36 5 Microprocessor Interface ..................................................................................................................................... 38 5.1 Intel/Motorola Protocol Selector ....................................................................................................................38 5.2 Word/Byte Addressing Selector ....................................................................................................................38 5.3 Access Via the Microprocessor Bus ............................................................................................................. 39 5.3.1 Microprocessor Interface Register Map ........................................................................................... 40 5.3.2 Register Space Access ....................................................................................................................44 5.3.3 Connection Memory Space Access .................................................................................................44 5.3.4 Data Memory Space Access ........................................................................................................... 45 5.3.5 Virtual Channel Memory Space Access ..........................................................................................45 6 Operating Control and Status .............................................................................................................................. 46 6.1 Control Registers .......................................................................................................................................... 46 6.1.1 Reset Registers ............................................................................................................................... 46 6.1.2 Master Output Enable Register ....................................................................................................... 47 6.1.3 Connection Control--Virtual Channel Enable and Data Memory Selector Register ........................ 48 6.1.4 General Clock Control (Phase Alignment, Fallback, Watchdogs) Register ..................................... 49 6.1.5 Phase Alignment Select Register .................................................................................................... 50 6.1.6 Fallback Control Register ................................................................................................................ 50 6.1.7 Fallback Type Select Register ......................................................................................................... 51 6.1.8 Fallback Trigger Registers ...............................................................................................................51 6.1.9 Watchdog Select, C8, and NETREF Registers ................................................................................ 52
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Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Table of Contents (continued)
Contents Page
6.1.10 Watchdog EN Register .................................................................................................................... 53 6.1.11 Failsafe Control Registers ................................................................................................................ 54 6.1.12 External Buffers--Descriptor Table Base Address .......................................................................... 55 6.2 Error and Status Registers ........................................................................................................................... 55 6.2.1 Clock Errors ..................................................................................................................................... 56 6.2.1.1 Transient Clock Errors Registers ......................................................................................... 56 6.2.1.2 Latched Clock Error Register .............................................................................................. 57 6.2.2 System Status .................................................................................................................................. 58 6.2.3 Clock Fallback Status Register ........................................................................................................ 58 6.2.4 PLL and Switching Status Register ..................................................................................................58 6.2.5 System Errors Register .................................................................................................................... 59 6.2.6 Device Identification Registers .........................................................................................................60 6.2.7 Miscellaneous Status ....................................................................................................................... 61 7 Clock Architecture ...............................................................................................................................................62 7.1 Clock Input Control Registers ....................................................................................................................... 63 7.1.1 Main Input Selector Register ............................................................................................................ 63 7.1.2 Main Divider Register ....................................................................................................................... 64 7.1.3 Analog PLL1 (APLL1) Input Selector Register ................................................................................. 64 7.1.4 APLL1 Rate Register ....................................................................................................................... 65 7.1.5 Main Inversion Select Register ........................................................................................................ 65 7.1.6 Resource Divider Register ............................................................................................................... 66 7.1.7 Analog PLL2 (APLL2) Rate Register ............................................................................................... 66 7.1.8 LREF Input Select Registers ............................................................................................................ 67 7.1.9 DPLL1 Input Selector ....................................................................................................................... 68 7.1.9.1 DPLL1 Rate Register ........................................................................................................... 68 7.1.10 DPLL2 Input Selector ....................................................................................................................... 69 7.1.10.1 DPLL2 Rate Register ........................................................................................................... 69 7.1.11 NETREF1 Registers ........................................................................................................................ 70 7.1.12 NETREF2 Registers ........................................................................................................................ 71 7.2 Clock Output Control Registers .................................................................................................................... 72 7.2.1 Master Output Enables Register ...................................................................................................... 72 7.2.2 Clock Output Format Registers ........................................................................................................ 74 7.2.3 TCLK and L_SCx Select Registers ..................................................................................................74 7.3 Clock Register Access .................................................................................................................................. 76 7.4 Clock Circuit Operation--APLL1 .................................................................................................................. 76 7.4.1 Main Clock Selection, Bit Clock, and Frame ....................................................................................76 7.4.1.1 Watchdog Timers ................................................................................................................ 77 7.4.1.2 Frame Center Sampling ...................................................................................................... 78 7.4.2 Main and Resource Dividers ............................................................................................................ 78 7.4.3 DPLL1 .............................................................................................................................................. 79 7.4.4 Reference Selector .......................................................................................................................... 79 7.4.5 Internal Clock Generation ................................................................................................................ 79 7.4.5.1 Phase Alignment ................................................................................................................. 80 7.5 Clock Circuit Operation, APLL2 .................................................................................................................... 81 7.5.1 DPLL2 .............................................................................................................................................. 81 7.6 Clock Circuit Operation, CT_NETREF Generation ....................................................................................... 81 7.6.1 NETREF Source Select ................................................................................................................... 81 7.6.2 NETREF Divider .............................................................................................................................. 81 7.7 Clock Circuit Operation--Fallback and Failsafe ...........................................................................................82
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
Table of Contents (continued)
Contents
7.7.1
Page
Clock Fallback ................................................................................................................................. 82 7.7.1.1 Fallback Events ................................................................................................................... 82 7.7.1.2 Fallback Scenarios--Fixed vs. Rotating Secondary ............................................................ 83 7.7.1.3 H-Bus Clock Enable/Disable on Fallback ............................................................................ 86 7.7.2 Clock Failsafe ..................................................................................................................................88 7.7.2.1 Failsafe Events ....................................................................................................................88 8 Frame Group and FG I/O .................................................................................................................................... 90 8.1 Frame Group Control Registers ....................................................................................................................90 8.1.1 FGx Lower and Upper Start Registers ............................................................................................. 90 8.1.2 FGx Width Registers ........................................................................................................................ 91 8.1.3 FGx Rate Registers ......................................................................................................................... 91 8.2 FG7 Timer Option ......................................................................................................................................... 92 8.2.1 FG7 Counter (Low and High Byte) Registers .................................................................................. 92 8.3 FGIO Control Registers ................................................................................................................................ 93 8.3.1 FGIO Data Register ......................................................................................................................... 93 8.3.2 FGIO Read Mask Register .............................................................................................................. 93 8.3.3 FGIO R/W Register .......................................................................................................................... 94 8.4 FG Circuit Operation ..................................................................................................................................... 95 8.4.1 Frame Group 8 kHz Reference Generation .....................................................................................96 8.4.2 FGIO General-Purpose Bits ............................................................................................................. 97 8.4.3 Programmable Timer (FG7 Only) .................................................................................................... 97 8.4.4 FG External Interrupts ..................................................................................................................... 97 8.4.5 FG Diagnostic Test Point Observation ............................................................................................97 9 General-Purpose I/O ........................................................................................................................................... 98 9.1 GPIO Control Registers ................................................................................................................................ 98 9.1.1 GPIO Data Register ......................................................................................................................... 98 9.1.2 GPIO Read Mask Register .............................................................................................................. 99 9.1.3 GPIO R/W Register ......................................................................................................................... 99 9.1.4 GPIO Override Register ................................................................................................................. 100 9.2 GP Circuit Operation ................................................................................................................................... 100 9.2.1 GPIO General-Purpose Bits .......................................................................................................... 101 9.2.2 GP Dual-Purpose Bits GPIO (Override) ......................................................................................... 101 9.2.2.1 GP H.110 Clock Master Indicators (GP0, GP1 Only) ........................................................ 101 9.2.2.2 PCI_RST# Indicator (GP2 Only) ........................................................................................101 9.2.3 GP External Interrupts ................................................................................................................... 101 9.2.4 GP Diagnostic Test Point Observation ..........................................................................................101 10 Stream Rate Control ....................................................................................................................................... 102 10.1 H-Bus Stream Rate Control Registers ................................................................................................... 103 10.1.1 H-Bus Rate Registers ....................................................................................................................103 10.2 L-Bus Stream Rate Control Registers ................................................................................................... 103 10.2.1 L-Bus Rate Registers ..................................................................................................................... 103 10.2.2 L-Bus 16.384 Mbits/s Operation .................................................................................................... 104 10.2.3 16.384 Mbits/s Local I/O Superrate ...............................................................................................105 11 Minibridge ........................................................................................................................................................107 11.1 Wait-State Control Registers ................................................................................................................. 107 11.1.1 Minibridge Wait-State Control Registers ........................................................................................107 11.2 Strobe Control Registers ....................................................................................................................... 110 11.3 Minibridge Circuit Operation ..................................................................................................................110 11.4 Minibridge Operational Addressing ....................................................................................................... 112
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Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Table of Contents (continued)
Contents Page
12 Error Reporting and Interrupt Control .............................................................................................................. 113 12.1 Interrupt Control Registers .................................................................................................................... 113 12.1.1 Interrupts Via External FG[7:0] Registers ...................................................................................... 113 12.1.1.1 FGIO Interrupt Pending Register ....................................................................................... 113 12.1.2 Interrupts Via External GP[7:0] ...................................................................................................... 115 12.1.2.1 GPIO Interrupt Pending Register ....................................................................................... 115 12.1.2.2 GPIO Edge/Level and GPIO Polarity Registers ................................................................ 116 12.1.3 Interrupts Via Internal System Errors ............................................................................................. 116 12.1.4 System Interrupt Pending High/Low Registers .............................................................................. 117 12.1.5 System Interrupt Enable High/Low Registers ................................................................................ 118 12.1.6 Interrupts Via Internal Clock Errors ................................................................................................119 12.1.7 Clock Interrupt Pending High/Low Registers ................................................................................. 120 12.1.8 Clock Interrupt Enable High/Low Registers ................................................................................... 121 12.1.9 Interrupt Servicing Registers .......................................................................................................... 122 12.1.9.1 Arbitration Control Register ............................................................................................... 122 12.1.10 PCI_INTA Output Select Register .................................................................................................. 122 12.1.10.1 SYSERR and CLKERR Output Select Register ................................................................ 122 12.1.10.2 Interrupt In-Service Registers ........................................................................................... 123 12.2 Error Reporting and Interrupt Controller Circuit Operation .................................................................... 125 12.2.1 Externally Sourced Interrupts Via FG[7:0], GP[7:0] ....................................................................... 126 12.2.2 Internally Sourced System Error Interrupts ....................................................................................126 12.2.3 Internally Sourced Clock Error Interrupts ....................................................................................... 126 12.2.4 Arbitration of Pending Interrupts .................................................................................................... 126 12.2.4.1 Arbitration Off .................................................................................................................... 126 12.2.4.2 Flat Arbitration ...................................................................................................................126 12.2.4.3 Tier Arbitration ...................................................................................................................126 12.2.4.3.1 Pre-Empting Disabled ..................................................................................127 12.2.4.3.2 Pre-Empting Enabled ..................................................................................127 12.2.5 CLKERR Output ............................................................................................................................. 127 12.2.6 SYSERR Output ............................................................................................................................ 127 12.2.7 PCI_INTA# Output ......................................................................................................................... 127 12.2.8 System Handling of Interrupts ........................................................................................................ 127 13 Test and Diagnostics ....................................................................................................................................... 128 13.1 Diagnostics Control Registers ............................................................................................................... 128 13.1.1 FG Testpoint Enable Register ........................................................................................................ 128 13.1.2 GP Testpoint Enable Register .......................................................................................................129 13.1.3 State Counter Modes Registers .....................................................................................................132 13.1.4 Miscellaneous Diagnostics Low Register ....................................................................................... 133 13.1.5 External Buffer Retry Timer Register ............................................................................................. 134 13.2 Diagnostic Circuit Operation .................................................................................................................. 135 14 Connection Control--Standard and Virtual Channel ............................................................................... ....... 136 14.1 Programming Interface ..........................................................................................................................136 14.1.1 PCI Interface .................................................................................................................................. 136 14.1.1.1 PCI Connection Memory Programming .............................................................................136 14.1.1.2 PCI Virtual Channel Memory Programming ......................................................................138 14.1.2 Microprocessor Interface ............................................................................................................... 139 14.1.2.1 Microprocessor Connection Memory Programming ..........................................................139 14.1.2.2 Microprocessor Virtual Channel Memory Programming ............................................... 144 14.2 Switching Operation .............................................................................................................................. 146
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
Table of Contents (continued)
Contents Page
14.2.1 Memory Architecture and Configuration ........................................................................................146 14.2.1.1 Connection Memory .......................................................................................................... 146 14.2.1.1.1 Virtual Channel Switching, Nonbonded Connections .................................. 147 14.2.1.1.2 Virtual Channel Switching, Bonded Connections ........................................ 147 14.2.1.2 Data Memory ..................................................................................................................... 148 14.2.1.3 Virtual Channel Memory .................................................................................................... 149 14.2.2 Standard Switching ........................................................................................................................ 149 14.2.2.1 Constant Delay and Minimum Delay Connections ............................................................ 149 14.2.2.2 Pattern Mode ..................................................................................................................... 149 14.2.2.3 Subrate .............................................................................................................................. 149 14.2.2.3.1 Subrate Switching Overview ........................................................................ 150 14.2.2.3.2 Subrate Switching Using T8110 .................................................................. 151 14.2.2.3.3 Subrate Packing of Outgoing Bytes ............................................................. 152 14.2.2.3.4 Subrate Unpacking of Incoming Bytes ........................................................ 153 14.2.3 Virtual Channel (Packet Payload) Switching ................................................................................. 155 14.2.3.1 Nonbonded Channels ........................................................................................................ 155 14.2.3.2 Subrate .............................................................................................................................. 157 14.2.3.3 Bonded Channels .............................................................................................................. 158 14.2.3.4 External Buffer Access ......................................................................................................160 14.2.3.4.1 Overview ......................................................................................................160 14.2.3.4.2 Descriptor Table ..........................................................................................161 14.2.3.4.3 External Buffer ............................................................................................. 162 14.2.3.4.4 Transfer Protocol ......................................................................................... 162 14.2.3.4.5 External Buffer Data Transfer ...................................................................... 164 14.2.3.4.6 Descriptor Table Update .............................................................................. 164 14.2.3.5 T8110 Packet Switching, Circuit Operation .......................................................................164 14.2.3.5.1 System Errors Due to Packet Switching ...................................................... 165 15 Electrical Characteristics ................................................................................................................................. 166 15.1 Absolute Maximum Ratings ................................................................................................................... 166 15.1.1 Handling Precautions ..................................................................................................................... 166 15.2 Crystal Specifications ............................................................................................................................ 166 15.2.1 XTAL1 Crystal ................................................................................................................................166 15.2.2 XTAL2 Crystal ................................................................................................................................167 15.2.3 Reset Pulse ................................................................................................................................... 168 15.3 Thermal Considerations for the 272 PBGA ........................................................................................... 168 15.4 dc Electrical Characteristics ..................................................................................................................168 15.4.1 PCI Signals .................................................................................................................................... 168 15.4.2 Electrical Drive Specifications, CT_C8 and /CT_FRAME .............................................................. 168 15.4.3 All Other Pins ................................................................................................................................. 169 15.5 H-Bus Timing ......................................................................................................................................... 169 15.5.1 Timing Diagrams ............................................................................................................................ 169 15.6 ac Electrical Characteristics ..................................................................................................................170 15.6.1 Skew Timing, H-Bus ...................................................................................................................... 170 15.7 Hot-Swap ............................................................................................................................................... 171 15.7.1 LPUE (Local Pull-Up Enable) ........................................................................................................ 171 15.8 Decoupling ............................................................................................................................................171 15.9 APLL VDD Filter ...................................................................................................................................... 171 15.10 PC Board PBGA Considerations ........................................................................................................... 172 15.11 Unused Pins .......................................................................................................................................... 172
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Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Table of Contents (continued)
Contents Page
15.12 T8110 Evaluation Boards ...................................................................................................................... 172 15.13 T8110 Ordering Information .................................................................................................................. 172 16 Package Outline .............................................................................................................................................. 173 16.1 Pin and Pad Assignments ..................................................................................................................... 173 17 JTAG/Boundary Scan ..................................................................................................................................... 177 17.1 The Principle of Boundary-Scan Architecture ........................................................................................ 177 17.1.1 Instruction Register ........................................................................................................................ 178 17.2 Boundary-Scan Register ....................................................................................................................... 178 Appendix A. Constant and Minimum Connections ................................................................................................190 A.1 Connection Definitions ...............................................................................................................................190 A.2 Delay Type Definitions ...............................................................................................................................190 Appendix B. Register Bit Field Mnemonic Summary ............................................................................................. 193
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
2 Pin Description
2.1 Interface Signals
Table 1. Interface Signals Signal PCI_AD PCI_CBE# PCI_CLK PCI_DEVSEL# PCI_FRAME# PCI_GNT# PCI_IDSEL PCI_INTA# PCI_IRDY# PCI_LOCK# PCI_PAR PCI_PERR# PCI_REQ# PCI_RST# PCI_SERR# PCI_STOP# PCI_TRDY# I/O I/O I/O In I/O I/O In In Out I/O In I/O I/O Out In Out I/O I/O Width 32 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Function PCI bus address/data. PCI bus command/byte enable. PCI bus clock (33 MHz). PCI bus device select. PCI bus cycle frame. PCI bus grant. PCI bus initialization device select. PCI bus interrupt. PCI bus initiator ready. PCI bus lock. PCI bus parity. PCI bus parity error. PCI bus request. PCI bus reset. PCI bus system error. PCI bus stop. PCI bus target ready.
Table 2. Minibridge Interface Signals Signal MB_A I/O I/O Width 16 Minibridge Function Address[15:0] out. Note: Special power-on function for PCI core EEPROM. MB_A[3] = EE_SK_OUT MB_A[2] = EE_DI_OUT MB_A[1] = EE_DO_IN Data bus I/O. Read strobe output. Write strobe output. Chip select 0 output. Chip select 1 output. Chip select 2 output. Chip select 3 output. Chip select 4 output. Chip select 5 output. Chip select 6 output. Chip select 7 output. Microprocessor Interface Function Address[15:0] in.
MB_D MB_RD MB_WR MB_CS0 MB_CS1 MB_CS2 MB_CS3 MB_CS4 MB_CS5 MB_CS6 MB_CS7
I/O I/O I/O I/O I/O I/O I/O I/O I/O Out I/O
16 1 1 1 1 1 1 1 1 1 1
Data bus in/out. RDn(DSn) in. WRn(R/Wn) in. Address[16] in. Address[17] in. Address[18] in. Address[19] in. CSn in. Word/byte select in. RDY(DTACKn) out. Intel*/Motorola select in.
* Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc.
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Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
2 Pin Description (continued)
Table 3. H-Bus (H.100/H.110 Interface) Signals Signal VPRECHARGE H110_ENABLE H100_ENABLE CT_D CT_C8_A /CT_FRAME_A CT_C8_B /CT_FRAME_B CT_NETREF1 CT_NETREF2 /C16+ /C16- /C4 C2 SCLK /SCLKx2 /FR_COMP I/O In In In I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Width 1 1 1 32 1 1 1 1 1 1 1 1 1 1 1 1 1 Function Precharge voltage for pull-downs, H.110 bus signals: CT_D, CT_NETREF1, CT_NETREF2. Pull-down enable for H.110 bus signals: CT_D, CT_NETREF1, CT_NETREF2. Pull-up enable for H.100 bus signals: CT_D, CT_NETREF1, CT_NETREF2, CT_C8_A, CT_C8_B, /CT_FRAME_A, /CT_FRAME_B. H.100/H.110 bus data. H.100/H.110 bit clock A. H.100/H.110 frame reference A. H.100/H.110 bit clock B. H.100/H.110 frame reference B. H.100/H.110 network reference 1. H.100/H.110 network reference 2. H-MVIP* compatibility clock (16.384 MHz, differential). H-MVIP compatibility clock (16.384 MHz, differential). MVIP compatibility clock (4.096 MHz). MVIP compatibility clock (2.048 MHz). SC-bus compatibility clock. SC-bus compatibility clock. Compatibility frame reference.
* MVIP is a trademark of Natural MicroSystems Corporation.
Table 4. L-Bus (Local) Interface Signals Signal L_D L_SC FG I/O I/O Out I/O Width 32 4 8 Local bus data. Local bus clock outputs. Local frame groups. Function
Table 5. Clock Circuit Interface Signals Signal XTAL1_IN XTAL1_OUT XTAL2_IN XTAL2_OUT I/O In Out In Out Width 1 1 1 1 Function Crystal oscillator #1 input (16.384 MHz). Crystal oscillator #1 feedback. Crystal oscillator #2 input (6.176 MHz or 12.352 MHz). Crystal oscillator #2 feedback.
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
2 Pin Description (continued)
Table 5. Clock Circuit Interface Signals (continued) Signal LREF TCLK_OUT PRI_REF_OUT PRI_REF_IN NR1_SEL_OUT NR1_DIV_IN NR2_SEL_OUT NR2_DIV_IN I/O In Out Out In Out In Out In Width 8 1 1 1 1 1 1 1 Function Local clock reference inputs. Internal chip clock output. Main divider reference out for CLAD/DJAT. CLAD/DJAT reference in for APLL1. CT_NETREF1 selection out for CLAD/DJAT. CLAD/DJAT reference in for CT_NETREF1 divider. CT_NETREF2 selection out for CLAD/DJAT. CLAD/DJAT reference in for CT_NETREF2 divider.
Table 6. GPIO Interface Signals Signal GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7 I/O I/O I/O I/O I/O I/O I/O I/O I/O Width 1 1 1 1 1 1 1 1 GPIO Function GPIO bit 0 I/O GPIO bit 1 I/O GPIO bit 2 I/O GPIO bit 3 I/O GPIO bit 4 I/O GPIO bit 5 I/O GPIO bit 6 I/O GPIO bit 7 I/O Alternate Function A-master indicator out. B-master indicator out. Forwarded PCI_RST# out. -- -- -- -- --
Table 7. Miscellaneous Interface Signals Signal RESET# SYSERR CLKERR LPUE EE_CS VIO/P_SELECT I/O In Out Out In Out In Width 1 1 1 1 1 1 Function Chip reset. System error indicator. Clocking error indicator. Pull-up enable for signals: FG, GP, L_D, LREF, MB_D, NR1_DIV_IN, NR2_DIV_IN, PRI_REF_IN. EEPROM chip select. PCI bus environment, apply GND for microprocessor interface, apply 3.3 V or 5 V for PCI interface.
Table 8. JTAG Signals Signal TRST# TCK TMS TDI TDO I/O In In In In Out Width 1 1 1 1 1 JTAG reset. JTAG clock. JTAG mode select. JTAG data in. JTAG data out. Function
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Agere Systems Inc.
Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
2 Pin Description (continued)
2.2 T8110 Pinout Information
The T8110 package is a 272-pin PBGA ball grid array. Refer to the table below for ball assignment, buffer type, and pull-up/pull-down information. Note: The pull-up/down column in the following table is defined as follows:
n 20 k down--20 k pull-down resistor is always in-circuit. n 50 k up--50 k pull-up resistor is always in-circuit. n LPUE: 50 k up--when LPUE = 1, a 50 k pull-up resistor is in-circuit. n Enabled: 50 k up/20 k Vpre--when H100_ENABLE = 1, a 50 k pull-up resistor is in-circuit (see Figure 2 on
page 18). When H110_ENABLE = 1, a 20 k pull-down resistor from the VPRECHARGE input to this signal is in-circuit. Table 9. T8110 Pinouts PCI Interface Ball Y18 W17 V16 U16 Y17 Y16 W16 V15 Y15 W15 W14 V14 Y14 Y13 W13 V13 Y9 W9 V9 V8 Y8 W8 W7 V7 Y7 Y6 Pin Name PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 Buffer Type PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O Pull-Up/Down -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
2 Pin Description (continued)
Table 9. T8110 Pinouts (continued) PCI Interface (continued) Ball W6 V6 Y5 W5 V5 V4 U14 U12 U9 U7 Y3 W11 Y10 W4 W10 Y4 Y11 V10 U11 W12 W3 Y2 V12 V11 Y12 F1 G1 K3 J3 K1 K2 L3 L4 G2 G3 H1 Pin Name PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_CBE0# PCI_CBE1# PCI_CBE2# PCI_CBE3# PCI_CLK PCI_DEVSEL# PCI_FRAME# PCI_GNT# PCI_IDSEL PCI_INTA# PCI_IRDY# PCI_LOCK# PCI_PAR PCI_PERR# PCI_REQ# PCI_RST# PCI_SERR# PCI_STOP# PCI_TRDY# MB_A0/UP_AO MB_A1/UP_A1/EE_DO MB_A10/UP_A10 MB_A11/UP_A11 MB_A12/UP_A12 MB_A13/UP_A13 MB_A14/UP_A14 MB_A15/UP_A15 MB_A2/UP_A2/EE_DI MB_A3/UP_A3/EE_SK MB_A4/UP_A4 Buffer Type PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI input PCI I/O PCI I/O PCI input PCI input PCI output/open drain PCI I/O PCI input PCI I/O PCI I/O PCI output PCI input PCI output/open drain PCI I/O PCI I/O Minibridge Interface 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA I/O-Schmitt I/O-Schmitt I/O-Schmitt I/O-Schmitt I/O-Schmitt I/O-Schmitt I/O-Schmitt I/O-Schmitt I/O-Schmitt I/O-Schmitt I/O-Schmitt 20 k 20 k 20 k 20 k 20 k 20 k 20 k 20 k 20 k 20 k 20 k down down down down down down down down down down down Pull-Up/Down (see note on page 11) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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Agere Systems Inc.
Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
2 Pin Description (continued)
Table 9. T8110 Pinouts (continued) Minibridge Interface (continued) Ball H2 H3 J4 J1 J2 W1 V1 V2 U3 U1 U2 T3 T4 T1 T2 R3 P4 R1 R2 P2 P3 N1 P1 L1 L2 M1 M2 M3 M4 N2 N3 C1 D5 D7 A11 B11 C10 C11 A10 B10 Pin Name MB_A5/UP_A5 MB_A6/UP_A6 MB_A7/UP_A7 MB_A8/UP_A8 MB_A9/UP_A9 MB_D0 MB_D1 MB_D2 MB_D3 MB_D4 MB_D5 MB_D6 MB_D7 MB_D8 MB_D9 MB_D10 MB_D11 MB_D12 MB_D13 MB_D14 MB_D15 MB_RD/UP_RD#(DS#) MB_WR/UP_WR#(R/W#) MB_CS0/UP_A16 MB_CS1/UP_A17 MB_CS2/UP_A18 MB_CS3/UP_A19 MB_CS4/UP_CSN MB_CS5/UP_WB_SEL MB_CS6/UP_RDY(DTACK#) MB_CS7/IM_SEL VPRECHARGE H110_ENABLE H100_ENABLE CT_D0 CT_D1 CT_D2 CT_D3 CT_D4 CT_D5 Buffer Type 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA 3-state 8 mA I/O-Schmitt H-Bus Interface Op amp noninvert Input Input PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O -- 20 k down 20 k down Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Pull-Up/Down (see note on page 11) 20 k down 20 k down 20 k down 20 k down 20 k down LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up 20 k down 20 k down 20 k down 20 k down LPUE: 50 k up LPUE: 50 k up External pull-up required LPUE: 50 k up
Vpre Vpre Vpre Vpre Vpre Vpre
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
2 Pin Description (continued)
Table 9. T8110 Pinouts (continued) H-Bus Interface (continued) Ball B9 C9 A9 B8 C8 A8 C7 A7 B7 C6 A6 B6 C5 A5 B5 A4 B4 C4 A3 B3 C3 A2 B2 B1 C2 D2 A13 A12 B13 B12 A14 B14 D9 D10 D12 D14 C14 C13 C12 Pin Name CT_D6 CT_D7 CT_D8 CT_D9 CT_D10 CT_D11 CT_D12 CT_D13 CT_D14 CT_D15 CT_D16 CT_D17 CT_D18 CT_D19 CT_D20 CT_D21 CT_D22 CT_D23 CT_D24 CT_D25 CT_D26 CT_D27 CT_D28 CT_D29 CT_D30 CT_D31 CT_C8_A /CT_FRAME_A CT_C8_B /CT_FRAME_B CT_NETREF1 CT_NETREF2 /C16+ /C16- /C4 C2 SCLK /SCLKX2 /FR_COMP Buffer Type PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O 24 mA I/O-Schmitt 24 mA I/O-Schmitt 24 mA I/O-Schmitt 24 mA I/O-Schmitt PCI I/O PCI I/O 24 mA I/O-Schmitt 24 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 24 mA I/O-Schmitt 24 mA I/O-Schmitt 24 mA I/O-Schmitt Pull-Up/Down (see note on page 11) Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up/20 k Enabled: 50 k up Enabled: 50 k up Enabled: 50 k up Enabled: 50 k up Enabled: 50 k up/20 k Enabled: 50 k up/20 k 50 k up 50 k up 50 k up 50 k up 50 k up 50 k up 50 k up Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre Vpre
Vpre Vpre
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Agere Systems Inc.
Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
2 Pin Description (continued)
Table 9. T8110 Pinouts (continued)
L-Bus Interface Ball J20 J19 J18 K17 K20 K19 K18 L18 L20 L19 M18 M17 M20 M19 N19 N18 N20 P20 P19 P18 R20 R19 R18 P17 T20 T19 T18 U20 V20 U19 U18 T17 H20 H19 H18 G19 Y20 Y19 W20 W19 W18 V19 V18 V17 Pin Name LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23 LD24 LD25 LD26 LD27 LD28 LD29 LD30 LD31 L_SC0 L_SC1 L_SC2 L_SC3 FG0 FG1 FG2 FG3 FG4 FG5 FG6 FG7 Buffer Type 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA 3-state 8 mA 3-state 8 mA 3-state 8 mA 3-state 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt Pull Up/Down (see note on page 11) LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k -- -- -- -- LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k LPUE: 50 k up up up up up up up up up up up up up up up up up up up up up up up up up up up up up up up up
up up up up up up up up
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
2 Pin Description (continued)
Table 9. T8110 Pinouts (continued) Clock Circuit Interface
Ball Pin Name Buffer Type Pull Up/Down (see note on page 11)
B20 C19 E20 F19 A15 B15 C15 C16 A16 B16 B17 C17 G20 A17 A18 B18 A19 D19 C20 D1 E1 E2 F2 D3 F3 E3 E4 Y1 V3 W2 J17 G4 U5 C18 E18 D18 F18 G18
XTAL1_IN XTAL1_OUT XTAL2_IN XTAL2_OUT LREF0 LREF1 LREF2 LREF3 LREF4 LREF5 LREF6 LREF7 TCLK_OUT PRI_REF_OUT PRI_REF_IN NR1_SEL_OUT NR1_DIV_IN NR2_SEL_OUT NR2_DIV_IN GP0/AMASTER GP1/BMASTER GP2/FWD_PCIRST# GP3 GP4 GP5 GP6 GP7 RESET# SYSERR CLKERR LPUE EE_CS VIO/P_SELECT TRST# TCK TMS TDI TDO
Input Crystal feedback Input Crystal feedback Input-Schmitt Input-Schmitt Input-Schmitt Input-Schmitt Input-Schmitt Input-Schmitt Input-Schmitt Input-Schmitt 8 mA 3-state 8 mA 3-state Input-Schmitt 8 mA 3-state Input-Schmitt 8 mA 3-state Input-Schmitt GPIO Interface 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt Miscellaneous Interfaces Input-Schmitt 8 mA 3-state 8 mA 3-state Input 8 mA 3-state -- JTAG Interface Input-Schmitt Input-Schmitt Input-Schmitt Input-Schmitt 4 mA 3-state
-- -- -- -- LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up -- -- LPUE: 50 k up -- LPUE: 50 k up -- LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up LPUE: 50 k up 50 k up -- -- 50 k up -- 20 k down 50 k 50 k 50 k 50 k -- up up up up
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Agere Systems Inc.
Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
2 Pin Description (continued)
Table 9. T8110 Pinouts (continued) Power
Ball Pin Name Buffer Type Pull Up/Down
B19 E19 D6 D11 D15 F4 F17 K4 L17 R4 R17 U6 U10 U15 A1 D4 D8 D13 D17 H4 H17 N4 N17 U4 U8 U13 U17 J9--12 K9--12 L9--12 M9--12 A20 D16 D20 E17 F20 G17
APLL1VDD APLL2VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Analog VDD Analog VDD -- -- -- -- -- -- -- -- -- -- -- -- Ground
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- Thermal Ground -- -- -- -- -- -- -- -- No Connects No connects must be left unconnected.
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
2 Pin Description (continued)
2.3 Special Buffer Requirements
2.3.1 H1x0 Bus Signal Internal Pull-Up/Pull-Down The H1x0 bus pins require special consideration for H.100 and H.110 usage. There are two control pins to select between various internal bus pull-ups/pull-downs, as shown below:
n H100_ENABLE. Enables internal 50 k pull-ups on CT_Dn, CT_NETREF1, CT_NETREF2, CT_C8_A,
CT_C8_B, /CT_FRAME_A, and /CT_FRAME_B signals.
n H110_ENABLE. Enables internal 20 k pull-downs on all 32 CT_Dn signals, CT_NETREF1, and CT_NETREF2
to the VPRECHARGE signal. Note: The two H1x0 enables are active-high. Only one or the other should ever be asserted. Warning: Do not assert both at the same time. Please refer to Figure 2 for more detail.
CT_Dn, CT_NETREF1, CT_NETREF2 VDD 50 k, MIN
PAD
20 k, MIN TO OTHER CT_Dn
PAD
APPLY 0.7 V, NOMINAL VPRECHARGE H100_ENABLE H110_ENABLE
PAD
PAD
VDD 50 k, MIN
PAD
CT_C8_A, CT_C8_B, /CT_FRAME_A, /CT_FRAME_B
5-9611 (F)
Figure 2. T8110 Pull-Up/Pull-Down Arrangement for H1x0 Pins
2.3.2 Local Bus Signal Internal Pull-Up The LPUE input is active-high; and is used to activate pull-ups on the following local signals: GP[7:0], FG[7:0], MB_D[15:0], LD[31:0], LREF[7:0], PRI_REF_IN, NR1_DIV_IN, and NR2_DIV_IN.
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Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
3 Main Architectural Features
3.1 T8110 Architecture
The T8110 includes all of the clocking and standard switching functions found on previous Ambassador devices, plus additional functionalities which are described in the following sections. There are two architectures: PCI (see Section 4 on page 22) and microprocessor (see Section 5 on page 38). The local PCI bus interface allows the T8110 to act as a target (access control registers, memories, etc.) and as an initiator. The T8110 performs standard H-bus/L-bus switching, and the capability of the initiator allows an interface for switching packet payloads to/from the H-bus/L-bus; see Section 14, starting on page 136, for more details. With this architecture selection, the minibridge port converts PCI target accesses into a simple handshake, and passes these accesses to external devices connected to this port; see Section 11, starting on page 107. The microprocessor bus interface allows the T8110 to perform standard H-bus/L-bus switching (i.e., there is no packet payload switching between the H-bus/L-bus and the microprocessor port). With this architecture, the minibridge port is used as the microprocessor bus port, and the PCI interface is ignored.
LOCAL CLOCKS FRAME GROUPS AND GP I/O H1x0 CLOCKS
CLOCKING AND TIMING CONTROL FG FRAME TIMING GROUPS ADDITIONAL I/O
VIRTUAL CHANNEL CONTROLLER
PARALLEL-TO-SERIAL CONVERSION (OUTPUT) SERIAL-TO-PARALLEL CONVERSION (INPUT)
INTERNAL CLOCKS
H1x0 EVEN CONNECTION MEMORY H1x0 ODD CONNECTION MEMORY LOCAL HIGH CONNECTION MEMORY LOCAL LOW CONNECTION MEMORY
DATA MEMORY CONTROLLER
H1x0 STREAMS (BIDIRECTIONAL)
ERROR SIGNALS
INTERRUPT AND ERROR CONTROL
CLOCK ERRORS
DATA MEMORY 2K x 8 DATA MEMORY 2K x 8
SYSTEM ERRORS GENERALPURPOSE I/O
LOCAL STREAMS (BIDIRECTIONAL)
GENERALPURPOSE I/O
REGISTER ACCESS CONTROL BRIDGE SIGNALS MINIBRIDGE
CONNECTION MEMORY CONTROLLER
PCI MASTER/SLAVE CORE WITH BURST
(LOCAL) PCI BUS 5-8920 (F)
Figure 3. T8110 Block Diagram
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
3 Main Architectural Features (continued)
H.100 CLOCKS, LOCAL CLOCKS
16.384 MHz
6.176 MHz OR 12.352 MHz
VALID FLAG STORE H.100 EVEN CONNECTION MEMORY
JTAG/SCAN PORT
FRAME GROUPS
FRAME GRP
VALID FLAG STORE APLL1 TIMING DERIVATION APLL2 H.100 ODD CONNECTION MEMORY VALID FLAG STORE FRAME SYNC 16.384 MHz LOCAL HI CONNECTION MEMORY VALID FLAG STORE LOCAL LOW CONNECTION MEMORY
MEMORY BIST CONTROLLER
SCAN INTERFACE
DATA MEMORY ACCESS SCHEDULER
LOCAL INTERRUPTS, ERROR FLAGS
65.536 MHz INTERRUPT CONTROLLER RESETN
DATA PAGE 1 LO DATA PAGE 1 HI VCMEM DATA PAGE 2
PARALLEL-TO-SERIAL (OUTPUT) SERIAL-TO-PARALLEL (INPUT) CONVERSION
32.768 MHz
STATIC
SCRATCH
SETUP/CONTROL REGISTERS GENERAL-PURPOSE I/O GENERAL-PURPOSE REGISTER
VIRTUAL CHANNEL MEMORY ACCESS CONTROLLER
PULL FIFO
REGISTER ACCESS CONTROLLER
CONNECTION MEMORY ACCESS CONTROLLER
DATA MEMORY ACCESS CONTROLLER (DIAGNOSTICS)
PUSH FIFO
DATA MEMORY ACCESS CONTROLLER (PACKET SWITCH)
NOTIFY FIFO
NOTIFY PENDING
MINIBRIDGE PORT
TARGET BUS
INITIATOR BUS
LOCAL BUS BRIDGE CONTROLLER
PCI CORE
EEPROM I/F
PCI BUS
5-9423a (F)
Figure 4. T8110 Architecture 1--PCI Bus Interface
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LOCAL STREAMS (BIDIRECTIONAL)
H.100 STREAMS (BIDIRECTIONAL)
Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
3 Main Architectural Features (continued)
JTAG/SCAN PORT
H.100 CLOCKS, LOCAL CLOCKS
16.348 MHz
6.176 MHz OR 12.352 MHz
VALID FLAG STORE H.100 EVEN CONNECTION MEMORY
FRAME GROUPS
FRAME GRP
VALID FLAG STORE APLL1 TIMING DERIVATION APLL2 H.100 ODD CONNECTION MEMORY VALID FLAG STORE FRAME SYNC 16.384 MHz LOCAL HI CONNECTION MEMORY VALID FLAG STORE LOCAL LOW CONNECTION MEMORY
MEMORY BIST CONTROLLER
SCAN INTERFACE
DATA MEMORY ACCESS SCHEDULER
LOCAL INTERRUPTS, ERROR FLAGS
65.536 MHz INTERRUPT CONTROLLER RESETN
DATA PAGE 1 LO DATA PAGE 1 HI DATA PAGE 2
PARALLEL-TO-SERIAL (OUTPUT) SERIAL-TO-PARALLEL (INPUT) CONVERSION
32.768 MHz
SETUP/CONTROL REGISTERS GENERAL-PURPOSE I/O GENERAL-PURPOSE REGISTER
REGISTER ACCESS CONTROLLER
CONNECTION MEMORY ACCESS CONTROLLER
DATA MEMORY ACCESS CONTROLLER (DIAGNOSTICS)
MINIBRIDGE PORT
TARGET BUS
MICROPROCESSOR INTERFACE
PCI CORE NO CONNECTION
EEPROM I/F
PCI BUS 5-9424 (F)
Figure 5. T8110 Architecture 2--Microprocessor Bus Interface
Agere Systems Inc.
LOCAL STREAMS (BIDIRECTIONAL)
H.100 STREAMS (BIDIRECTIONAL)
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
4 PCI Interface
The T8110 provides a selection of two interface mechanisms via the VIO/P_SELECT input. This must be a static signal (either pulled high or pulled low).
n VIO/P_SELECT tied to GND = T8110 interface to a microprocessor bus, connected via the minibridge port. n VIO/P_SELECT tied to 3.3 V = T8110 interface to a local PCI bus, 3.3 V signaling. n VIO/P_SELECT tied to 5 V = T8110 interface to a local PCI bus, 5 V signaling.
The T8110 is a single-function PCI device; it can act as a target or an initiator. All addressing is DWORD aligned for 32-bit data transfers. Refer to Section 2.1 on page 8 for pin descriptions. When the PCI interface is selected, the minibridge port functions as a bridge to convert the PCI access protocol into a simple handshake protocol for external, non-PCI devices connected to this port. For more details, see Section 11, starting on page 107. The PCI interface is arranged to provide a mixture of accesses. Initialization and register programming is typically under coprocessor control. As a result, the T8110 operates as a slave when being programmed by the coprocessor or by the host via a PCI-PCI bridge. Diagnostics and error handling are also defined as slave operations. However, when packets are processed by either taking data from the H1x0 bus and passing it to memory, or when data is retrieved from memory and sent to the H1x0 bus, the T8110 operates as a master, arbitrating for the bus and taking control of its own burst transactions. This ensures that the bandwidth required by the T8110 as a local PCI bus owner is kept to a minimum. Packet transactions are not limited to the H1x0 bus and local time slots can be routed to and from the PCI bus as well.
4.1 Target
The T8110 PCI bus interface allows target access to five internal regions: registers, connection memory, data memory, virtual channel memory, and the minibridge. Target burst transactions are only allowed to the register and connection memory space. No target bursts are allowed to/from the data memory, virtual channel memory, or the minibridge space. All target accesses get synchronized between the PCI's 33 MHz clock domain and the T8110's internal 65.536 MHz clock domain. Of the 32 bits of address provided, the upper 12 decode the base address, while the lower 20 provide addressing for the internal regions of the T8110, as shown in Table 10. Table 10. T8110 Memory Mapping to PCI Space Region Registers Subregion Reserved Operating control and status Clocks Rate control Frame group General-purpose I/O Interrupt control Minibridge control Reserved -- -- -- -- -- -- -- Range (hex) 0x00000--0x000FF 0x00100--0x001FF 0x00200--0x002FF 0x00300--0x003FF 0x00400--0x004FF 0x00500--0x005FF 0x00600--0x006FF 0x00700--0x007FF 0x00800--0x0FFFF 0x10000--0x1FFFF 0x20000--0x2FFFF 0x30000--0x3FFFF 0x40000--0x4FFFF 0x50000--0x6FFFF 0x70000--0x7FFFF 0x80000--0xFFFFF
Virtual channel memory Data memory Reserved Connection memory Reserved Minibridge Reserved
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4.1.1 PCI Interface Registers Table 11. PCI Interface Registers Map DWORD Section Address Cross (20 bits) Reference 0x00100 6.1.1, 6.1.2 Registers Byte 3 Master enable Byte 2 Reserved Clock register access select Fallback trigger, lower Watchdog EN, lower Failsafe threshold low Status 2, latched clock errors, lower Status 6, system errors, lower Device ID, lower Reserved Diag2 Diag6 Reserved APLL1 input selector Reserved DPLL1 input selector DPLL2 input selector NETREF1 LREF select NETREF2 LREF select /FR_COMP width TCLK select L_SC2 select H-bus rate F/E L-bus rate F/E Byte 1 Reset select Data memory mode select Fallback type select Watchdog select, NETREF Failsafe enable and status Status 1, transient clock errors, upper Status 5 Reserved Status 9 Diag1 Diag5 Reserved Main divider Resource divider Reserved Reserved NETREF1 divider NETREF2 divider NETREF output enables Reserved L_SC1 select H-bus rate D/C L-bus rate D/C Byte 0 Soft reset VCSTART Fallback control Watchdog select, C8
0x00104 6.1.3, 6.1.4 Phase alignment select 0x00108 0x0010C 0x00110 0x00114 0x00120 0x00124 0x00128 0x0012C 0x00140 0x00144 0x00148 0x00200 0x00204 0x00208 0x0020C 0x00210 0x00214 0x00220 0x00224 0x00228 0x00300 0x00320 6.1.4 6.1.4 14.2.3.4.2 4.1.5 6.2.1 6.2.2, 6.2.5 6.2.6 6.2.6 13.1 13.1 13.1 7.1 7.1 7.1 7.1 7.1 7.1 7.2 7.2 7.2 10.1 10.2 Fallback trigger, upper Watchdog EN, upper
External buffers descriptor table--base address register[31:0] Reserved Status 3, latched clock errors, upper Status 7, system errors, upper Device ID, upper Reserved Diag3 Diag7 Reserved APLL1 rate APLL2 rate DPLL1 rate DPLL2 rate Reserved Reserved C8 output rate SCLK output rate L_SC3 select H-bus rate H/G L-bus rate H/G Failsafe control Status 0, transient clock errors, lower Status 4 Version ID Status 8 Diag0 Diag4 Diag8 Main input selector Main inversion select LREF input select LREF inversion select NETREF1 input selector NETREF2 input selector Master output enables CCLK output enables L_SC0 select H-bus rate B/A L-bus rate B/A
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Table 11. PCI Interface Registers Map (continued) DWORD Section Address Cross (20 bits) Reference 0x00400 0x00410 0x00420 0x00430 0x00440 0x00450 0x00460 0x00470 0x00474 0x00480 0x00500 0x00600 0x00604 0x00608 0x0060C 0x00610 0x00614 0x006FC 0x00700 0x00704 0x00710 0x00714 0x00720 0x00724 0x00730 0x00734 0x00740 0x00744 0x00750 8.1 8.1 8.1 8.1 8.1 8.1 8.1 8.1 8.2 8.3 9.1 12.1 12.1 12.1 12.1 12.1 12.1 12.1 11.1 11.1 11.1 11.1 11.1 11.1 11.1 11.1 11.1 11.1 11.1 Registers Byte 3 FG0 rate FG1 rate FG2 rate FG3 rate FG4 rate FG5 rate FG6 rate FG7 rate FG7 mode upper Reserved GPIO override FGIO interrupt polarity GPIO interrupt polarity System interrupt enable, upper Clock interrupt enable, upper CLKERR output select CLKERR pulse width In-service, byte 3 CS0 address hold wait CS1 address hold wait CS2 address hold wait CS3 address hold wait CS4 address hold wait Byte 2 FG0 width FG1 width FG2 width FG3 width FG4 width FG5 width FG6 width FG7 width FG7 mode lower FGIO R/W GPIO R/W Reserved Reserved System interrupt enable, lower Clock interrupt enable, lower SYSERR output select SYSERR pulse width In-service, byte 2 Byte 1 FG0 upper start FG1 upper start FG2 upper start FG3 upper start FG4 upper start FG5 upper start FG6 upper start FG7 upper start FG7 counter high byte FGIO read mask GPIO read mask FGIO interrupt enable GPIO interrupt enable System interrupt pending, upper Clock interrupt pending, upper PCI_INTA output select Reserved In-service, byte 1 Byte 0 FG0 lower start FG1 lower start FG2 lower start FG3 lower start FG4 lower start FG5 lower start FG6 lower start FG7 lower start FG7 counter low byte FGIO data register GPIO data register FGIO interrupt pending GPIO interrupt pending System interrupt pending, lower Clock interrupt pending, lower Arbitration control Reserved In-service, byte 0
CS0 address setup wait CS0 read hold wait CS0 read width wait CS0 read setup wait CS0 write hold wait CS0 write width wait CS0 write setup wait CS1 write hold wait CS1 write width wait CS1 write setup wait CS2 write hold wait CS2 write width wait CS2 write setup wait CS3 write hold wait CS3 write width wait CS3 write setup wait CS4 write hold wait CS4 write width wait CS4 write setup wait CS1 address setup wait CS1 read hold wait CS1 read width wait CS1 read setup wait CS2 address setup wait CS2 read hold wait CS2 read width wait CS2 read setup wait CS3 address setup wait CS3 read hold wait CS3 read width wait CS3 read setup wait CS4 address setup wait CS4 read hold wait CS4 read width wait CS4 read setup wait CS5 address setup wait CS5 read hold wait CS5 read width wait CS5 read setup wait
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Table 11. PCI Interface Registers Map (continued) DWORD Section Address Cross (20 bits) Reference 0x00754 0x00760 0x00764 0x00770 0x00774 0x00780 11.1 11.1 11.1 11.1 11.1 11.1 Registers Byte 3 CS5 address hold wait CS6 address hold wait CS7 address hold wait Reserved Byte 2 Byte 1 Byte 0
CS5 write hold wait CS5 write width wait CS5 write setup wait CS6 write hold wait CS6 write width wait CS6 write setup wait CS7 write hold wait CS7 write width wait CS7 write setup wait Reserved RD-WR strobe inversion CS strobe inversion
CS6 address setup wait CS6 read hold wait CS6 read width wait CS6 read setup wait CS7 address setup wait CS7 read hold wait CS7 read width wait CS7 read setup wait
PCI_CLK
PCI_AD[31:0]
ADDR
DATA
PCI_CBE#[3:0]
MEM_WR (0x7)
BYTE ENABLES
PCI_PAR
ADDR PARITY
DATA PARITY
PCI_FRAME#
PCI_IRDY#
PCI_IDSEL/SCAN_EN#
PCI_DEVSEL#
PCI_TRDY#
PCI_STOP# 5-9612 (F)
Notes: T8110 PCI I/F has medium decode speed. There is always a two-cycle turnaround between assertion of PCI_ FRAME# and assertion of PCI_DEVSEL#. All memory writes get posted to the T8110. Turnaround time for a single cycle write is three PCI clocks.
Figure 6. T8110 PCI Interface--Single Write Cycle
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PCI_CLK PCI_AD[31:0] PCI_CBE#[3:0] PCI_PAR PCI_FRAME# PCI_IRDY# PCI_IDSEL PCI_DEVSEL# PCI_TRDY# PCI_STOP#
ADDR MEM_WR XXXXX DATA 1 BYTE ENABLE 1 Addr Parity DATA 2 BEn 2 DATA 3 BEn 3 Data Parity 2 DATA n-2 BEn n-2 Data Parity n-3 DATA n-1 BEn n-1 Data Parity n-2 DATA n BEn n Data Parity n-1 Data Parity n
DATA PARITY 1
Notes: T8110 PCI I/F has medium decode speed. There is always a two-cycle turnaround between assertion of PCI_FRAME# and assertion of PCI_DEVSEL#. All memory writes get posted to the T8110. Turnaround time for the first data phase write is three PCI clocks. PCI core write FIFO depth = 8, so up to 8 data words can immediately get posted. For register region access, the application side operates at a faster rate than the PCI side, so the write FIFO will never become full, and PCI_TRDY# will remain active. For connection memory access, the application side operates slightly slower than the PCI side, so it is possible to fill the write FIFO. In this case, the PCI_TRDY# signal is deasserted while the application side catches up.
Figure 7. T8110 PCI Interface--Burst Write Cycle
PCI_CLK PCI_AD[31:0] PCI_CBE#[3:0] PCI_PAR PCI_FRAME# PCI_IRDY# PCI_IDSEL PCI_DEVSEL# PCI_TRDY# PCI_STOP# INITIAL TARGET LATENCY = 10 to 12 clocks (typical)
Notes: T8110 PCI I/F has medium decode speed. There is always a two-cycle turnaround between assertion of PCI_FRAME# and assertion of PCI_DEVSEL#. Turnaround time for memory reads from the T8110 is variable, depending on the region being accessed, and the synchronization time across the PCI clock and application clock domains. Initial target latency is typically between 10--12 PCI clock cycles.
ADDR MEM_RD (0x6) XXXXX Addr Parity XXXXXXXXXXXXXXXXXXX BYTE ENABLE XXXXXXXXXXXX BYTE ENABLE Data Parity DATA
XXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXX
Figure 8. T8110 PCI Interface--Single Read Cycle
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PCI_CLK PCI_AD[31:0] PCI_CBE#[3:0] PCI_PAR PCI_FRAME# PCI_IRDY# PCI_IDSEL PCI_DEVSEL# PCI_TRDY# PCI_STOP# INITIAL TARGET LATENCY = 10 TO 12 CLOCKS (TYPICAL)
ADDR MEM_RD (0x6)
XXXXX
Byte Enable 1 Addr Parity
DATA 1 BEn 1
DATA 2 BEn 2 Data Parity 1
DATA n-1 BEn n-1 Data Parity n-2
DATA n BEn n Data Parity n-1 Data Parity n
XXXXX
XXXXX
XXXXX
Notes: T8110 PCI I/F has medium decode speed. There is always a two-cycle turnaround between assertion of PCI_FRAME# and assertion of PCI_DEVSEL#. Turnaround time for memory reads from the T8110 is variable, depending on the region being accessed, and the synchronization time across the PCI clock and application clock domains. Initial target latency is typically between 10--12 PCI clock cycles. PCI core read FIFO depth = 8. For register region access, the application side operates at a faster rate than the PCI side, so the read FIFO will never become empty, and burst read data is returned as quickly as the PCI bus can accept it. For connection memory access, the application side operates slightly slower than the PCI side, so it is possible to empty the read FIFO. In this case, the PCI_TRDY# signal is deasserted while the application side catches up.
Figure 9. T8110 PCI Interface--Burst Read Cycle
PCI_CLK PCI_AD[31:0] PCI_CBE#[3:0] PCI_PAR PCI_FRAME# PCI_IRDY# PCI_IDSEL PCI_DEVSEL# PCI_TRDY# PCI_STOP# INITIAL TARGET LATENCY = 8 TO 10 CLOCKS (TYPICAL)
ADDR MEM_RD (0x6)
XXXXXXXXXXXXXXXXXX BYTE ENABLE
Addr Parity
XXXXXXXXXXXX BYTE ENABLE XXXXXXXXXXXXXXXXXXXXXXX
XXXXX
XXXXXXXXXXXXXXXXXX
Notes: T8110 PCI I/F has medium decode speed. There is always a two-cycle turnaround between assertion of PCI_FRAME# and assertion of PCI_DEVSEL#. Turnaround time for memory read RETRY is variable, depending on the region being accessed, and the synchronization time across the PCI clock and application clock domains. Initial target latency for a RETRY is typically between 8--10 PCI clock cycles.
Figure 10. T8110 PCI Interface--Delayed Read Cycle (Retry)
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PCI_CLK PCI_AD[31:0] PCI_CBE#[3:0] PCI_PAR PCI_FRAME# PCI_IRDY# PCI_IDSEL PCI_DEVSEL# PCI_TRDY# PCI_STOP# ADDR MEM_RD (0x6) XXXXXXXXXXX
Addr Parity
XXXXXXXXXXXXXXXXXXXXXXXX BYTE ENABLE XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Notes: T8110 PCI I/F has medium decode speed. There is always a two-cycle turnaround between assertion of PCI_FRAME# and assertion of PCI_DEVSEL#. Turnaround time for memory read target ABORT is 4 PCI clocks.
Figure 11. T8110 PCI Interface--Target Abort (Address Parity Error)
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4.1.2 Register Space Target Access The T8110 registers are always immediately available for access. Read and write bursting is allowed to this region. Read access to reserved addresses returns 0x00. For more details on register programming; refer to Section 6, starting on page 46, through Section 13, and to Figure 6 on page 25, through Figure 9. A detected address parity error on any read transaction results in a target abort; refer to Figure 11 on page 28. Address parity errors on write transactions are still posted to the PCI core interface, but are discarded. For burst transactions to the register space, the application side of the PCI core interface operates faster than the PCI bus, so the PCI core interface FIFOs will never get full. PCI_TRDY# remains asserted for all valid data phases applied. 4.1.3 Connection Memory Space Target Access The T8110 connection memory is always immediately available for access (via dedicated access times assigned for PCI bus target transactions). Read and write bursting is allowed to this region. For more details on connection memory programming, see Section 14.1 on page 136, and Figure 6 through Figure 9. A detected address parity error on any read transaction results in a target abort; refer to Figure 11. Address parity errors on write transactions are still posted to the PCI core interface, but are discarded. For burst transactions to the connection memory space, the application side of the PCI core interface operates slightly slower than the PCI bus, so the PCI core interface FIFOs may get full. In this case, PCI_TRDY# gets deasserted until the application side catches up. 4.1.4 Data Memory Space Target Access The T8110 data memory is not guaranteed to be immediately available for access. Access to data memory is prioritized for standard H-bus/L-bus switching and packet payload switching, with PCI target access allowed as the lowest priority. Because there is an indeterminate amount of latency, target burst transfers are not allowed to the data memory. Upon reception of a PCI read or write request, if the data memory is immediately available, the transaction is completed as normal single-cycle access; refer to Figure 6 and Figure 7. If the data memory is not available at the time of the request, any write cycle is posted and any read cycle becomes a delayed read. A detected address parity error on any read transaction results in a target abort (refer to Figure 11 on page 28). Address parity errors on write transactions are still posted to the PCI core interface, but are discarded. 4.1.4.1 Posted Write Transaction Only one posted write to the data memory may be queued at a time; refer to Figure 6 for more details. The user must monitor a status bit (register status 8, bit 0; refer to Section 6.2.7) to determine whether a posted write is already queued before attempting more writes. Subsequent posted write attempts to the data memory while a queued posted write has not completed result in an error condition, and both writes (the queued one and the subsequent one) are ignored. Error is reported at register status 7, bit 0 (refer to Section 6.2.5 on page 59). Subsequent read attempts from the data memory while a posted write is queued result in a target RETRY; please refer to Figure 10.
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4.1.4.2 Delayed Read Transaction Only one delayed read from the data memory may be queued at a time. A delayed read transaction latches the address and command information, and issues a retry back to the initiator (refer to Figure 10). If the initiator retries the same transaction or attempts a different read transaction from data memory prior to the queued delayed read completion, a retry is issued. The delayed read transaction is completed when the initiator retries the same transaction after the queued delayed read has finished (i.e., a normal completion of a single-cycle read; please refer to Figure 8). Any subsequent posted write attempts to the data memory while a delayed read is in progress result in an error condition, and the delayed read and the posted write attempts are ignored. Error is reported at register status 7, bit 0 (refer to Section 6.2.5 on page 59). 4.1.5 Virtual Channel Memory Space Target Access The T8110 virtual channel memory is not guaranteed to be immediately available for access. Access to this memory is prioritized for H-bus/L-bus switching and packet payload switching with PCI target access allowed as the lowest priority. Because there is an indeterminate amount of latency, target burst transfers are not allowed to the virtual channel memory. Upon reception of a PCI read or write request, if the virtual channel memory is immediately available, the transaction is completed as normal single-cycle access (refer to Figure 6 and Figure 8). If the virtual channel memory is not available at the time of the request, any write cycle is posted and any read cycle becomes a delayed read (for more detail on virtual channel memory programming; refer to Section 14.1.1.2 on page 138). A detected address parity error on any read transaction results in a target abort (refer to Figure 11). Address parity errors on write transactions are still posted to the PCI core interface, but are discarded. 4.1.5.1 Posted Write Transaction Only one posted write to the virtual channel memory may be queued at a time. Refer to Figure 6. The user must monitor a status bit (register status 8, bit 1; refer to Section 6.2.7) to determine whether a posted write is already queued before attempting more writes. Subsequent posted write attempts to the virtual channel memory while a queued posted write has not completed result in an error condition, and both writes (the queued one and the subsequent one) are ignored. Error is reported at register status 7, bit 1 (refer to Section 6.2.5 on page 59). Subsequent read attempts from the virtual channel memory while a posted WRITE is queued result in a target retry (refer to Figure 10). 4.1.5.2 Delayed Read Transaction Only one delayed read from the virtual channel memory may be queued at a time. A delayed read transaction latches the address and command information, and issues a retry back to the initiator (refer to Figure 10). If the initiator retries the same transaction or attempts a different read transaction from virtual channel memory prior to the queued delayed read completion, a retry is issued. The delayed read transaction is completed when the initiator retries the same transaction after the queued delayed read has finished (i.e., a normal completion of a single-cycle read; refer to Figure 8). Any subsequent posted write attempts to the virtual channel memory while a delayed read is in progress result in an error condition, and the delayed read and the posted write attempts are ignored. Error is reported at register status 7, bit 1 (refer to Section 6.2.5 on page 59). 4.1.6 Minibridge Space Target Access The T8110 minibridge port is not guaranteed to be immediately available for access. Access time to this space is dependent on wait-state control register setups. Because there is a potential variable amount of latency, target burst transfers are not allowed to the minibridge port. All write cycles are posted writes. All read cycles are delayed reads. Refer to the Minibridge section, starting on page 107, for more details on minibridge control and operation. A detected address parity error on any read transaction results in a target abort (refer to Figure 11). Address parity errors on write transactions are still posted to the PCI core interface, but are discarded. 30 Agere Systems Inc.
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4.1.6.1 Posted Write Transaction Only one posted write to the minibridge port may be queued at a time; please refer to Figure 6. The user must monitor a status bit (register status 8, bit 2) to determine whether a posted write is already queued before attempting more writes. Subsequent posted write attempts to the minibridge port while a queued posted write has not completed result in an error condition. The queued write is allowed to complete, but the subsequent write is ignored. Error is reported at register status 7, bit 2 (refer to Section 6.2.5 on page 59). Subsequent read attempts from the minibridge port, while a posted write is queued, result in a target retry (refer to Figure 10). 4.1.6.2 Delayed Read Transaction Only one delayed read from the minibridge port may be queued at a time. A delayed read transaction latches the address and command information, and issues a retry back to the initiator (refer to Figure 10). If the initiator retries the same transaction or attempts a different read transaction from the minibridge port prior to the queued delayed read completion, a retry is issued. The delayed read transaction is completed when the initiator retries the same transaction after the queued delayed read has finished (i.e., a normal completion of a single-cycle read; refer to Figure 8). Any subsequent posted write attempts to the minibridge port while a delayed read is in progress result in an error condition. The delayed read is allowed to complete, but the write request is ignored. Error is reported at register status 7, bit 2 (refer to Section 6.2.5 on page 59).
4.2 Initiator
The T8110 can initiate PCI transactions in order to perform packet payload switching between the local PCI bus and the 64 H-bus/L-bus data streams. The T8110 initiates accesses in order to either send (or push) data received from H-bus/L-bus streams to an external data buffer, or to retrieve (or pull) data from an external data buffer to transmit out to the H-bus/L-bus streams. Each operation requires three PCI burst accesses. An external descriptor table provides current read/write pointer status to the external data buffer. The T8110 fetches pointer information from the descriptor table, transfers data to/from the external data buffer, and then updates the descriptor table pointer information. For more details, see Section 14.2.3 on page 155. 4.2.1 PUSH Operation (Upstream Transaction) The push operation takes data received from incoming H-bus/L-bus streams and passes it to an external data buffer. This is denoted as an upstream transaction. The three required T8110 initiated burst cycles are shown below. For more details, see Section 14.2.3 on page 155.
n Memory read burst (fetch the write pointer information from the descriptor table). n Memory write burst (upload the received H-bus/L-bus data to external data buffer). n Memory write burst (update the write pointer information in the descriptor table).
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PCI_CLK PCI_AD[31:0] PCI_CBE[3:0] a 6 d1 0 d2 a 7 data1 d2 0 dn a 7 data1 0
PCI_REQ# PCI_FRAME# PCI_IRDY#
PCI_DEVSEL# PCI_TRDY#
PCI BUS Arbitration
Descriptor Table Fetch (2 DWORD burst READ)
PCI BUS Arbitration
External Buffer Data Update (n DWORD burst WRITE)
PCI BUS Arbitration
Descriptor Table Update (1 DWORD WRITE) 1444
Notes: This diagram depicts a target with medium decode speed (two-cycle turnaround to assertion of PCI_DEVSEL#). Each of the three separate PCI transactions requires a PCI bus arbitration (PCI_REQ# active, system responds with PCI_GNT#).
Figure 12. T8110 PCI Interface, Initiated PUSH Operation
4.2.2 PULL Operation (Downstream Transaction) The pull operation takes data from an external data buffer and passes it to the T8110 data memory for transmission onto outgoing H-bus/L-bus streams. This is denoted as a downstream transaction. The three required T8110 initiated burst cycles are shown below. For more information, see Section 14.2.3 on page 155.
n Memory read burst (fetch the read pointer information from the descriptor table). n Memory read burst (download the external data buffer to T8110 data memory for transmission on
H-bus/L-bus streams).
n Memory write burst (update the read pointer information in the descriptor table).
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PCI_CLK PCI_AD[31:0] PCI_CBE[3:0] a 6 d1 0 d2 a 6 d1 d2 0 dn a 7 data1 0
PCI_REQ# PCI_FRAME# PCI_IRDY#
PCI_DEVSEL# PCI_TRDY#
PCI BUS Arbitration
Descriptor Table Fetch (2 DWORD burst READ)
PCI BUS Arbitration
External Buffer Data Fetch (n DWORD burst READ)
PCI BUS Arbitration
Descriptor Table Update (1 DWORD WRITE) 1445
Notes: This diagram depicts a target with medium decode speed (two-cycle turnaround to assertion of PCI_DEVSEL#). Each of the three separate PCI transactions requires a PCI bus arbitration (PCI_REQ# active, system responds with PCI_GNT#).
Figure 13. T8110 PCI Interface, Initiated PULL Operation
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4.3 Configuration Space/EEPROM Interface
The T8110 PCI interface operates at 33 MHz and is a single-function device. As a target, T8110 is a memorymapped device, and responds to memory write and memory read commands. Dual-address cycles are not supported (32-bit addressing only). As a master, T8110 generates memory write or memory read commands only, as single data phase burst cycles of two or more data phases. Table 12. T8110 PCI Configuration Registers Byte Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44--0xFF Description Device ID Vendor ID Status register Command register Class code Revision ID BIST Header type Latency timer Cacheline size Memory base address Reserved Reserved Reserved Reserved Reserved Reserved Subsystem ID Subsystem vendor ID Reserved Reserved Reserved MAX_LAT MIN_GNT Interrupt pin Interrupt line Reserved Retry timeout PCI_TRDY# timeout Reserved
Access to the configuration registers is shown in Figure 14 and in Figure 15. The configuration register contents include the following: Device ID = 0x8110, T8110 Vendor ID = 0x11C1, Agere Status register: [15]: Detected parity error [14]: Signaled system error [13]: Received master abort [12]: Received target abort [11]: Signaled target abort [10:9] = 01, T8110 DEVSEL# timing is medium [8]: Data parity reported [7] = 1, T8110 is fast back-to-back capable [6] = 0, T8110 does not support user-definable features [5] = 0, T8110 is not 66 MHz capable [4:0] = 00000, reserved
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Command register: [15:10] = 000000, reserved [9]: Fast back-to-back master enable [8]: System error enable [7] = 0, T8110 does not use stepping [6]: Parity error enable [5] = 0, T8110 disables palette snoop [4]: Memory write and invalidate enable [3] = 0, T8110 ignores special cycles [2]: Bus master enable [1]: Memory access enable [0]: I/O access enable Class code = 0x02800, network controller--other Revision ID = revision of the device BIST = 0x00 (no BIST) Header type = 0x00 Latency timer = value--T8110 as a master, number of cycles of retained bus ownership Memory base address = 0xXXX00000, bits 31:20 are R/W as the static base address, which defines a 1 Mbyte region of addressable space. Subsystem ID, subsystem vendor ID: user-definable, loaded from the EEPROM I/F at reset (refer to Section 4.3.1 on page 36). MAX_LAT = value--T8110 as a master, how often it requires access to the PCI bus MIN_GNT = value--T8110 as a master, how long it retains PCI bus ownership Interrupt pin = 0x01--T8110 uses INTA# Interrupt line = value, user-defined Retry timeout = value [default = 0x80]--T8110 as a master, the number of retries performed PCI_TRDY# timeout = value [default = 0x80]--T8110 as a master, how long it will wait for PCI_TRDY#
PCI_CLK PCI_AD[31:0] PCI_CBE#[3:0] PCI_PAR PCI_FRAME# PCI_IRDY# PCI_IDSEL PCI_DEVSEL# PCI_TRDY# PCI_STOP#
Notes: T8110 PCI I/F has medium decode speed. There is always a two-cycle turnaround between assertion of PCI_FRAME# and assertion of PCI_DEVSEL#. A configuration write access cycle takes five PCI clocks.
ADDR
CFG_WR (0xB)
DATA Byte Enable
Addr Parity
XXXXX
Data Parity
Figure 14. T8110 PCI Interface--Configuration WRITE Cycle
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4 PCI Interface (continued)
PCI_CLK PCI_AD[31:0] PCI_CBE#[3:0] PCI_PAR PCI_FRAME# PCI_IRDY# PCI_IDSEL PCI_DEVSEL# PCI_TRDY# PCI_STOP#
Notes: T8110 PCI I/F has medium decode speed. There is always a two-cycle turnaround between assertion of PCI_FRAME# and assertion of PCI_DEVSEL#. A configuration read access cycle takes six PCI clocks.
ADDR
CFG RD (0xA)
XXXXXXXXXXXXXXXXXX Byte Enable
Addr Parity
DATA
XXXXX
XXXXXXXXXXXXXXXXXXXXXXXXX
Data Parity
Figure 15. T8110 PCI Interface--Configuration READ Cycle
4.3.1 Loadable PCI Configuration Space Via EEPROM The T8110 allows a user-definable subsystem ID and subsystem vendor ID field (configuration space address 0x2C). Immediately after power-on reset or PCIRST#, the T8110's PCI core loads the read-only configuration registers sequentially from the first 64 bytes in the EEPROM. All values are ignored, except for the subsystem ID, subsystem vendor ID, MAX_LAT, MIN_GNT, and INTERRUPT_PIN (bytes 44--63). Ignored values (bytes 0--43) are don't care and exist simply as placeholders. During the EEPROM operation, all PCI target accesses to the T8110 result in a target retry. Note: If no EEPROM is present, internal pull-down resistors will set the values for subsystem ID, subsystem vendor ID, MAX_LAT, MIN_GNT, and INTERRUPT_PIN to zero. After the PCI core loads the values into configuration registers, this space is read-only. The only way to change the values from 0 is from an external EEPROM. Four pins are required for the EEPROM interface. The following pins are used for EEPROM just at power-on: MB_A[1] = EE_DO_IN (input, data output from EEPROM) MB_A[2] = EE_DI_OUT (output, data input to EEPROM) MB_A[3] = EE_SK_OUT (output, clock input to EEPROM) EE_CS_OUT = EE_CS_OUT (output, chip select input to EEPROM) The interface protocol follows the standard 93C46 EEPROM (refer to Figure 16). A state machine within the T8110's PCI core produces nine read cycles, one for each of the read-only configuration register fields. Only the subsystem ID, subsystem vendor ID, MAX_LAT, MIN_GNT, and interrupt pin fields are configurable. All other fields returned by the EEPROM are ignored, but must be present as placeholders.
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Table 13. PCI Configuration Space, EEPROM Map EEPROM Address[5:0] 000000 000010 001000 001010 001100 101100 101110 111100 111110 EEPROM Data[15:0] Device ID field Vendor ID field Class code field (upper 2 bytes) Class code field (lower byte) and revision ID field BIST and header fields Subsystem ID field Subsystem vendor ID field MAX_LAT and MIN_GNT fields Interrupt pin field
Note: The EEPROM is not write-accessible via the T8110. The T8110's PCI core only generates control signals to read the EEPROM.
EE_SK EE_CS EE_DI
OP CODE START BIT
A5
A4
A3
A2
A1
A0
ADDRESS
EE_DO
d15
d14
d13
d12
d11
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
leading 0
DATA
Notes: Signals output from T8110 are driven relative to the falling edge of EE_SK and are sampled by the EEPROM on the rising edge. Signals output from the EEPROM are driven relative to the rising edge of EE_SK and are sampled by the T8110 on the falling edge. Each read cycle takes 26 EE_SK clocks. There are nine read cycles in all generated by the T8110's PCI core. The following T8110 pinout is used for the EEPROM interface signals: SIGNAL NAME EE_CS_OUT MB_A3 MB_A2 MB_A1 EEPROM FUNCTION BALL ASSIGNMENT G4 EE_CS--chip select G3 EE_SK--clock G2 EE_DI--data in G1 EE_DO--data out
Figure 16. EEPROM Interface Protocol
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5 Microprocessor Interface
The T8110 provides a selection of two interface mechanisms via the VIO/P_SELECT input. This must be a static signal (either pulled high or pulled low).
n VIO/P_SELECT tied to GND = T8110 interface to a microprocessor bus, connected via the minibridge port. n VIO/P_SELECT tied to 3.3 V = T8110 interface to a local PCI bus, 3.3 V signaling. n VIO/P_SELECT tied to 5 V = T8110 interface to a local PCI bus, 5 V signaling.
The T8110 microprocessor bus interface allows access to the T8110 internal regions via the minibridge port; see Table 9 on page 11 for pin descriptions. There are two user-selectable input signals that set up the microprocessor interface, MB_CS7 (Intel/Motorola protocol select) and MB_CS5 (word/byte address select).
5.1 Intel/Motorola Protocol Selector
MB_CS7 = 1 is the default, if left unconnected, and selects an Intel handshake protocol. MB_CS7 = 0 selects a Motorola handshake protocol. Note: The MB_CS7 signal must be static (either pulled high or pulled low). Table 14. Intel/Motorola Protocol Selector
Intel/Motorola Protocol Selector
Signal MB_D[15:0] MB_A[15:0] MB_CS0 MB_CS1 MB_CS2 MB_CS3 MB_CS4 MB_CS6 MB_RD MB_WR MB_CS5 MB_CS7
Intel Mnemonic
D[15:0] A[15:0] A[16] A[17] A[18] A[19] CSn RDY RDn (read strobe) WRn (write strobe) Default Default
Motorola Mnemonic
D[15:0] A[15:0] A[16] A[17] A[18] A[19] CSn DTACKn DSn (data strobe) R/Wn (read/write selector) Default Default
5.2 Word/Byte Addressing Selector
MB_CS5 = 1 is the default, if left unconnected, and selects 16-bit word aligned addressing. MB_CS5 = 0 selects 8-bit byte aligned addressing. Note: The MB_CS5 signal may be static or dynamic in nature. If dynamic, MB_CS5 must follow the same timing requirements as the address bus. Word-aligned addressing produces 16-bit data transfers via MB_D[15:0]. Byte-aligned addressing produces 8-bit data transfers via MB_D[7:0] (MB_D[15:8] is unused). The T8110 internal data bus is 32 bits, so MB_A[1:0] address bits are decoded along with MB_CS5 to control a dword-to-word or dword-to-byte swap function back to the MB_D bus.
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5.3 Access Via the Microprocessor Bus
The T8110 microprocessor bus interface allows access to three internal regions: registers, connection memory, and data memory. The virtual channel memory can be made accessible via a special diagnostic mode setting. All microprocessor bus asynchronous strobes are synchronized to the T8110's internal 65.536 MHz clock domain. There are 20 address bits provided to address the internal regions and these are defined in Table 15. Table 15. T8110 Memory Mapping to Microprocessor Space Region Registers Subregion Reserved Operating control and status Clocks Rate control Frame group General-purpose I/O Interrupt control Reserved Reserved Virtual channel memory (diagnostic only) Data memory Reserved Connection memory Reserved -- -- -- -- -- Range (hex) 0x00000--0x000FF 0x00100--0x001FF 0x00200--0x002FF 0x00300--0x003FF 0x00400--0x004FF 0x00500--0x005FF 0x00600--0x006FF 0x00700--0x007FF 0x00800--0x0FFFF 0x10000--0x1FFFF 0x20000--0x2FFFF 0x30000--0x3FFFF 0x40000--0x4FFFF 0x50000--0xFFFFF
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5 Microprocessor Interface (continued)
5.3.1 Microprocessor Interface Register Map The T8110 registers map into the microprocessor bus space as follows. Table 16. Microprocessor Interface Register Map DWORD Cross Address Reference (20 bits) 0x00100 6.1.1, 6.1.2 0x00104 6.1.3, 6.1.4 0x00108 0x0010C 0x00114 0x00118 0x00120 6.1.4 6.1.4 4.1.5 6.1.11 6.2.1 Register Byte 3 Master enable Phase alignment select Fallback trigger, upper Watchdog EN, upper Reserved Reserved Status 3, latched clock errors, upper Status 7, system errors, upper Device ID, upper Diag3 Diag7 Diag11 APLL1 rate APLL2 rate DPLL1 rate DPLL2 rate Reserved Reserved C8 output rate SCLK output rate L_SC3 select H-bus rate H/G L-bus rate H/G FG0 rate Byte 2 Reserved Byte 1 Reset select Byte 0 Soft reset Reserved Fallback control Watchdog select, C8 Failsafe control OOL threshold low Status 0, transient clock errors, lower Status 4 Version ID Diag0 Diag4 Diag8 Main input selector Main inversion select LREF input select LREF inversion select NETREF1 input selector NETREF2 input selector Master output enables CCLK output enables L_SC0 select H-bus rate B/A L-bus rate B/A FG0 lower start
Clock register access Data memory mode select select Fallback trigger, lower Fallback type select Watchdog EN, lower Failsafe sensitivity OOL monitor Status 2, latched clock errors, lower Status 6, system errors, lower Device ID, lower Diag2 Diag6 Diag10 APLL1 input selector Reserved DPLL1 input selector DPLL2 input selector NETREF1 LREF select NETREF2 LREF select /FR_COMP width TCLK select L_SC2 select H-bus rate F/E L-bus rate F/E FG0 width Watchdog select, NETREF Failsafe enable OOL threshold high Status 1, transient clock errors, upper Status 5 Reserved Diag1 Diag5 Diag9 Main divider Resource divider Reserved Reserved NETREF1 divider NETREF2 divider NETREF output enables Reserved L_SC1 select H-bus rate D/C L-bus rate D/C FG0 upper start
0x00124 6.2.2, 6.2.5 0x00128 0x00140 0x00144 0x00148 0x00200 0x00204 0x00208 0x0020C 0x00210 0x00214 0x00220 0x00224 0x00228 0x00300 0x00320 0x00400 6.2.6 13.1 13.1 13.1 7.1 7.1 7.1 7.1 7.1 7.1 7.2 7.2 7.2 10.1 10.2 8.1
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Table 16. Microprocessor Interface Register Map (continued) DWORD Cross Address Reference (20 bits) 0x00410 0x00420 0x00430 0x00440 0x00450 0x00460 0x00470 0x00474 0x00480 0x00500 0x00600 0x00604 0x00608 0x0060C 0x00610 0x00614 0x006FC 8.1 8.1 8.1 8.1 8.1 8.1 8.1 8.2 8.3 9.1 14.1 12.1 12.1 12.1 12.1 12.1 12.1 Register Byte 3 FG1 rate FG2 rate FG3 rate FG4 rate FG5 rate FG6 rate FG7 rate FG7 mode upper Reserved GPIO override FGIO interrupt polarity GPIO interrupt polarity System interrupt enable, upper Clock interrupt enable, upper CLKERR output select In-service, byte 3 Byte 2 FG1 width FG2 width FG3 width FG4 width FG5 width FG6 width FG7 width FG7 mode lower FGIO R/W GPIO R/W Reserved Reserved System interrupt enable, lower Clock interrupt enable, lower SYSERR output select In-service, byte 2 Byte 1 FG1 upper start FG2 upper start FG3 upper start FG4 upper start FG5 upper start FG6 upper start FG7 upper start FG7 counter high byte FGIO read mask GPIO read mask FGIO interrupt enable GPIO interrupt enable System interrupt pending, upper Clock interrupt pending, upper PCI_INTA output select Reserved In-service, byte 1 Byte 0 FG1 lower start FG2 lower start FG3 lower start FG4 lower start FG5 lower start FG6 lower start FG7 lower start FG7 counter low byte FGIO data register GPIO data register FGIO interrupt pending GPIO interrupt pending System interrupt pending, lower Clock interrupt pending, lower Arbitration control Reserved In-service, byte 0
CLKERR pulse width SYSERR pulse width
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Microprocessor Access Read Cycle, Intel Protocol
taccess WORD/BYTE SELECT, A[19:0] ADDRESS VALID
CSn tas DSn tRDYhi tRDYlo RDY tah
tde D[15:0], READ CYCLE
tdv READ DATA VALID
tdz
5-9418 (F)
Microprocessor Access Write Cycle, Intel Protocol
taccess WORD/BYTE SELECT, A[19:0] ADDRESS VALID
CSn tas WRn tRDYhi tRDYlo RDY tds tdh WR DATA VALID
5-9419 (F)
tah
D[15:0], WRITE CYCLE
Figure 17. Microprocessor Access Timing, Intel Protocol
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Microprocessor Access Read Cycle, Motorola Protocol
taccess WORD/BYTE SELECT, A[19:0] ADDRESS VALID
R/Wn
CSn tas DSn tDTACKlo DTACKn tde D[15:0], READ CYCLE tdv READ DATA VALID
5-9416 (F)
tah
tDTACKhi
tdz
Microprocessor Access Write Cycle, Motorola Protocol
taccess WORD/BYTE SELECT, A[19:0] ADDRESS VALID
R/Wn
CSn tas DSn tDTACKlo DTACKn tds tdh WR DATA VALID
5-9417 (F)
tah
tDTACKhi
D[15:0], WRITE CYCLE
Figure 18. Microprocessor Access Timing, Motorola Protocol
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5.3.2 Register Space Access The T8110 registers are always immediately available for access, providing low latency time to acknowledge the transaction. Read access to [reserved] addresses returns 0x00. Register access timing for Figure 17 and Figure 18 is shown below. Table 17. Register Space Access Timing Name taccess tas tah tRDYlo tRDYhi tDTACKlo tDTACKhi tde tdv tdz tds tdh Overall Access Time Address Setup Time Address Hold Time Parameter Min (ns) 41 5 0 6 36 36 10 7 5 10 25 0 Max (ns) -- -- -- 12 72 70 15 14 9 16 -- --
Intel Cycle, Time to RDY Deasserted Intel Cycle, Time to RDY Reasserted Motorola Cycle, Time to DTACKn Asserted Motorola Cycle, Time to DTACKn Deasserted
Read Cycle, Time to Data Enabled Read Cycle, Time to Data Valid Read Cycle, Time to Data Invalid Write Cycle, Data Setup Time Write Cycle, Data Hold Time
5.3.3 Connection Memory Space Access The T8110 connection memory is always immediately available for access (via dedicated access times assigned for microprocessor transactions) providing low latency time to acknowledge the transaction. Connection memory access timing for Figure 17 and Figure 18 is shown below. Table 18. Connection Memory Space Access Timing Name taccess tas tah tRDYlo tRDYhi tDTACKlo tDTACKhi tde tdv tdz tds tdh Parameter Overall Access Time Address Setup Time Address Hold Time Intel Cycle, Time to RDY Deasserted Intel Cycle, Time to RDY Reasserted Motorola Cycle, Time to DTACKn Asserted Motorola Cycle, Time to DTACKn Deasserted Read Cycle, Time to Data Enabled Read Cycle, Time to Data Valid Read Cycle, Time to Data Invalid Write Cycle, Data Setup Time Write Cycle, Data Hold Time Min (ns) 41 5 0 6 36 36 10 7 5 10 25 0 Max (ns) -- -- -- 12 72 70 15 14 9 16 -- --
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5.3.4 Data Memory Space Access The T8110 data memory is not guaranteed to be immediately available for access. Access to data memory is prioritized for standard H-bus/L-bus switching, with microprocessor bus transaction access allowed as the lowest priority. The latency time to acknowledge these transactions is indeterminate and depends on the H-bus/L-bus switching configuration. Data memory access timing for Figure 17 and Figure 18 is shown below. Table 19. Data Memory Space Access Timing Name taccess tas tah tRDYlo tRDYhi tDTACKlo tDTACKhi tde tdv tdz tds tdh Parameter Overall Access Time Address Setup Time Address Hold Time Intel Cycle, Time to RDY Deasserted Intel Cycle, Time to RDY Reasserted Motorola Cycle, Time to DTACKn Asserted Motorola Cycle, Time to DTACKn Deasserted Read Cycle, Time to Data Enabled Read Cycle, Time to Data Valid Read Cycle, Time to Data Invalid Write Cycle, Data Setup Time Write Cycle, Data Hold Time Min (ns) 41 5 0 6 36 36 10 7 5 10 25 0 Max (ns) * -- -- 12 * * 15 14 9 16 -- --
* Max data memory space access time is indeterminate, and depends on how much of the data memory access bandwidth is being taken by TDM switch connections.
5.3.5 Virtual Channel Memory Space Access Microprocessor access to the virtual channel memory is provided for diagnostic purposes only and is disabled by default. Access to this region is enabled via the diagnostic registers; see Section 13 on page 128. The T8110 virtual channel memory is not guaranteed to be immediately available for access. Access to virtual channel memory is prioritized for standard H-bus/L-bus switching, with microprocessor bus transaction access allowed as the lowest priority. The latency time to acknowledge these transactions is indeterminate and depends on the H-bus/L-bus switching configuration. Virtual channel memory access timing for Figure 17 and Figure 18 is shown below. Table 20. Virtual Channel Memory Space Access Timing Name taccess tas tah tRDYlo tRDYhi tDTACKlo tDTACKhi tde tdv tdz tds tdh Parameter Overall Access Time Address Setup Time Address Hold Time Intel Cycle, Time to RDY Deasserted Intel Cycle, Time to RDY Reasserted Motorola Cycle, Time to DTACKn Asserted Motorola Cycle, Time to DTACKn Deasserted Read Cycle, Time to Data Enabled Read Cycle, Time to Data Valid Read Cycle, Time to Data Invalid Write Cycle, Data Setup Time Write Cycle, Data Hold Time Min (ns) 41 5 0 6 36 36 10 7 5 10 25 0 Max (ns) -- -- -- 12 57* 55* 15 14 9 16 -- --
* Immediate response, same as register access, assuming no virtual channel connections are programmed into the connection memory (virtual channels aren't supported with the microprocessor interface protocol selected).
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6 Operating Control and Status
Overall T8110 operational control and status is configured via registers occupying 0x00100--0x001FC in the address space.
6.1 Control Registers
General control functions are soft reset, reset configuration, overall master output enables, and data memory configuration. Clocking-specific general control functions are clock register access configuration, phase alignment, clock fallback, and clock watchdog configuration. Table 21. Control Register Map DWORD Address Byte 3 (20 bits) 0x00100 Master enable 0x00104 Phase alignment select 0x00108 Fallback trigger, upper 0x0010C Watchdog EN, upper 0x00110 0x00114 Register Byte 2 Reserved Clock register access select Fallback trigger, lower Watchdog EN, lower Byte 1 Reset select Data memory mode select Byte 0 Soft reset VCSTART*
Reserved
Fallback type select Fallback control Watchdog select, Watchdog select, C8 NETREF External buffers descriptor table--base address register [31:0]* Failsafe threshold low Failsafe enable and status Failsafe control
* VCSTART and external buffers descriptor table registers are only relevant if the T8110 interfaces to the PCI bus. If the selected T8110 interface is to the microprocessor bus, this register is [reserved].
6.1.1 Reset Registers The soft reset and reset select registers control soft reset functions and reset signal masking. Writes to the soft reset register trigger the corresponding action, and the set bit(s) are automatically cleared.
n Power-on reset: nonmaskable:
-- At power-on, initialize all T8110 registers (including reset select register) and connection valid flags, and initialize the T8110 PCI interface. The power-on reset cell test input is controlled via diagnostic register; see Section 13.
n Hard reset: maskable via reset select register, HRBEB:
-- On assertion of RESET#, initialize all T8110 registers (excluding reset select register) and connection valid flags.
n PCI reset: nonmaskable to PCI interface:
-- Maskable to T8110 back-end via reset select register, PRBEB. On assertion of PCI_RST#, initialize the T8110 PCI interface. If unmasked (PRBEB = 1), also initialize all T8110 registers (excluding reset select register) and connection valid flags. -- Maskable to minibridge port via reset select register, PMBEB. The PCI_RST# input to the T8110 can be forwarded to the minibridge port, using the GP(2) output (via register 0x00503; see Section 9.1 on page 98). Polarity of the forwarded reset is selectable (via register 0x00781; see Section 11.2 on page 110). Soft resets are maskable via reset select register, SRBEB, and selectable via soft reset register, SRESR.
n Soft reset 1: Initialize all T8110 registers (excluding reset select register) and connection valid flags. n Soft reset 2: Initialize all T8110 registers (excluding reset select register). n Soft reset 3: Reset all interrupt pending registers and the interrupt in-service register.
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n Soft reset 4: Reset the interrupt in-service register only. n RESET_PENDING_MEM: Reset the virtual channel NOTIFY_PENDING memory. n RESET_QUEUE: Reset the virtual channel NOTIFY_QUEUE FIFO.
Table 22. Reset Registers Byte Address Name Bit(s) Mnemonic 7:0 SRESR Value 0000 0000 0000 0001 0000 0010 0001 0000 0010 0000 0100 0000 1000 0000 0000 0 1 0 1 0 1 0 1 Function NOP (default value). Reset all registers and connection valid flags. Reset all registers. Reset interrupt pending and in-service registers. Reset interrupt in-service register only. Reset virtual channel NOTIFY_PENDING memory. Reset virtual channel NOTIFY_QUEUE. NOP (default). Disable PCI reset to minibridge (default). Enable PCI reset to minibridge. Disable PCI reset to back end (default). Enable PCI reset to back end. Disable hard reset to back end. Enable hard reset to back end (default). Disable soft resets to back end. Enable soft resets to back end (default).
0x00100 Soft Reset
0x00101 Reset Select
7:4 3 2 1 0
Reserved PMBEB PRBEB HRBEB SRBEB
6.1.2 Master Output Enable Register The master output enable register is used to control master output enables to various groups of T8110 signals, including the following: L-bus data streams (L_D[31:0]) L-bus clocks (L_SC[3:0], FG[7:0] when used as frame group outputs) H-bus data streams (CT_D[31:0]) H-bus clocks (CT_C8_A, /CT_FRAME_A, CT_C8_B, /CT_FRAME_B, CT_NETREF1,CT_NETREF2, /C16+, /C16-, /C4, C2, SCLK, /SCLKx2, /FR_COMP) GPIO (GP[7:0]) FGIO (FG[7:0] when used as programmable register outputs) Minibridge (MB_A[15:0], MB_CS[7:0], MB_RD, MB_WR, MB_D[15:0]) T8110 outputs that are not programmatically enabled (i.e., always driven except during reset) include the following: CLKERR, SYSERR, PRI_REF_OUT, NR1_SEL_OUT, and NR2_SEL_OUT.
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Table 23. Master Output Enable Register Byte Address Name Bit(s) 7 6 Mnemonic AIOEB MBREB Value 0 1 0 1 Function Individual enables via bits [6:0] (default). Enable all (same as bits [6:0] = 1111111). Disable minibridge* (default). Enable minibridge. Note: If AIOEB is set to 1 to enable all then MBREB must also be set to 1 to enable the minibridge. Disable FGIO (default). Enable FGIO. Disable GPIO (default). Enable GPIO. Disable H-bus clocks (default). Enable H-bus clocks. Disable H-bus data streams (default). Enable H-bus data streams. Disable L-bus clocks, L_SC, FG (default). Enable L-bus clocks. Disable L-bus data streams (default). Enable L-bus data streams.
0x00103 Master Enable
5 4 3 2 1 0
FGREB GPIEB HCKEB HDBEB LCKEB LDBEB
0 1 0 1 0 1 0 1 0 1 0 1
*MBREB is only relevant if the T8110 interfaces to the PCI bus. If the selected T8110 interface is to the microprocessor bus, this bit is reserved.
6.1.3 Connection Control--Virtual Channel Enable and Data Memory Selector Register The VC start register is used as an overall enable/disable for virtual channel switching activity, with the option to synchronize the enabling of switching activity with the internal 8 kHz frame reference (refer to Section 14.2.3 for more detail). Writes to the VC start register trigger the corresponding action, and the set bit(s) are automatically cleared. Table 24. Virtual Channel Enable and Data Memory Selector Register Byte Address Name Bit(s) 7:0 Mnemonic VCSSR Value 0000 0000 0001 0001 0000 0010 0000 0001 0001 0010 Function NOP (default). START (enable) VC switching, immediate. PAUSE (disable) VC switching, immediate. START VC switching, synchronized to frame. PAUSE VC switching, synchronized to frame.
0x00104 VCSTART
The data memory mode select register MSbit controls subrate switching enable. The lower 7 bits control the T8110 data memory switching configuration. For more details, see Section 14.2.1.2 on page 148. There are six data memory configurations as outlined below. (If the T8110 interfaces to the PCI bus, all configurations are valid. If the interface selection is to the microprocessor bus, only the standard switching configurations 1--3 are allowed.)
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1. 4k single-buffered switch. Standard H-bus/L-bus switching only, up to 4096 simplex connections, all connections are minimum delay due to single-buffer configuration. 2. 2k double-buffered switch. Standard H-bus/L-bus switching only, up to 2048 simplex connections, all connections are programmable for minimum or constant delay via the double-buffer configuration. 3. 2k single-buffered switch + 1k double-buffered switch. Standard H-bus/L-bus switching only, up to 2048 simplex minimum delay connections (single buffer) and up to 1024 simplex minimum or constant delay connections (double buffer). 4. 2k single-buffered switch + 256 virtual channels. Standard H-bus/L-bus switching, up to 2048 simplex minimum delay connections (single buffer), PLUS packet payload switching, up to 256 virtual channels. 5. 1k double-buffered switch + 256 virtual channels. Standard H-bus/L-bus switching, up to 1024 simplex minimum or constant delay connections (double buffer), PLUS packet payload switching, up to 256 virtual channels. 6. No standard switching + 512 virtual channels. Packet payload switching only, up to 512 virtual channels. Table 25. Data Memory Mode Select Register Byte Address Name Bit(s) Mnemonic 7 6:0 GSREB DMMSP Value 0 1 100 0000 010 0000 011 0000 010 0010 001 0010 000 0100 Function Disable subrate switching (default). Enable subrate switching. 4k single-buffer switch (default). 2k double-buffer switch. 2k single-buffer, 1k double-buffer switch. 2k single buffer switch, 256 virtual channels. 1k double buffer switch, 256 virtual channels. 512 virtual channels.
0x00105 Data Memory Mode Select
6.1.4 General Clock Control (Phase Alignment, Fallback, Watchdogs) Register The clock register access select register controls the selection between accessing the active vs. the inactive set of T8110 clock registers. The T8110 contains two sets of clock registers, X and Y. The X and Y register sets are comprised of the registers listed in Table 43 on page 63, Clock Input Control Register Map, and Table 56 on page 72, Clock Output Control Register Map. Only one set is used at a time. It is selected based on the clock fallback setup. The clock register set that is currently in use is denoted as the active set; see Section 7.3 on page 76 for more details. Table 26. Clock Register Access Select Register Byte Address Name Bit(s) Mnemonic 7:0 CSASR Value Function
0x00106 Clock Register Access Select
0000 0000 Access inactive clock registers (default). 0000 0001 Access active clock registers.
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6.1.5 Phase Alignment Select Register The phase alignment select register selects the phase alignment configuration. For more details, see Section 7.4.5.1 on page 80. The T8110 internally generates an 8 kHz frame reference. Shown below are three configurations to control phase alignment between this internally generated frame reference and a selected incoming frame reference from the H-bus (/CT_FRAME_A, /CT_FRAME_B, or /FR_COMP) or local clock reference (LREF[4:7]).
n Disable alignment, no realignment of unaligned frames n Snap alignment, immediate realignment of unaligned frames n Slide alignment, gradual realignment of unaligned frames
Table 27. Phase Alignment Select Register Byte Address Name Bit(s) Mnemonic 7:0 PAFSR Value Function
0x00107 Phase Alignment Select
0000 0000 Phase alignment is disabled (default). 0000 0001 Enable snap alignment. 0000 0010 Enable slide alignment.
6.1.6 Fallback Control Register The fallback control register allows user control over the active and inactive clock register sets. For more details, see Section 7.7.1 on page 82. Writes to the fallback control register trigger the corresponding action, and the set bit(s) are automatically cleared. The four commands are shown below:
n GO_CLOCKS. At initialization, the clock register Y set is active, the X set is inactive, and access is enabled to
the X set. The GO_CLOCKS command transitions the Y set to inactive and the X set to active. This command can either be performed immediately upon issue or can wait to be performed until the next 8 kHz frame reference (synchronized to frame).
n CLEAR_FALLBACK. Forces a state transition for active/inactive assignment of the clock register X and Y sets
after a fallback event has occurred. This command can either be performed immediately upon issue or can wait to be performed until the next 8 kHz frame reference (synchronized to frame).
n FORCE_FALLBACK. Forces a state transition for active/inactive assignment of the clock register X and Y sets
by creating a fallback event. This command can either be performed immediately upon issue or can wait to be performed until the next 8 kHz frame reference (synchronized to frame).
n COPY ACTIVE TO INACTIVE SET. Copies all register values in the current active clock register set to the inactive clock register set. This command is performed immediately upon issue.
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6 Operating Control and Status (continued)
Table 28. Fallback Control Register Byte Address Name Bit(s) Mnemonic 7:0 FBCSR Value 0000 0000 0000 0001 0000 0010 0000 0100 0001 0001 0001 0010 0001 0100 0010 0000 Function NOP (default). GO_CLOCKS command. CLEAR_FALLBACK command. FORCE_FALLBACK command. GO_CLOCKS synchronized to frame*. CLEAR_FALLBACK synchronized to frame*. FORCE_FALLBACK synchronized to frame*. COPY ACTIVE TO INACTIVE SET command.
0x00108 Fallback Control
* The synchronized to frame command also has a diagnostic element--instead of performing the command right at the frame boundary, the user can elect to perform the command at a specified offset time from the frame boundary, by programming the Diag11 and Diag10 registers, 0x0014B--0x0014A.
6.1.7 Fallback Type Select Register The upper nibble configures which H-bus clocks are selected to trigger a clock fallback event. Any of the legacy modes have predetermined trigger enables and ignore the fallback trigger register settings. Nonlegacy modes require the fallback trigger register settings. For more details, see Section 7.7.1 on page 82. The lower nibble configures the state machine that controls clock register set active/inactive assignments. There are three possible selections. For more details, see Section 7.7 on page 82.
n Disabled. No transitions of clock register X and Y sets to active/inactive. n Fixed secondary. Swap the active/inactive sets on a fallback event; swap them back when fallback is cleared. n Rotating secondary. Swap the active/inactive sets on a fallback event; maintain this state when fallback is
cleared. Table 29. Fallback Type Select Register Byte Address Name Bit(s) Mnemonic 7:4 FTRSN Value 0000 0001 0010 0100 1000 1001 0000 0001 0010 Function NOP (default). Legacy, fallback to OSC/4 on main select failure. Legacy, fallback X/Y set on main select failure. Legacy, fallback X/Y set on H-bus A/B failure. Fallback trigger registers control fallback. Fallback trigger registers control fallback and H-Bus clock enable state machine is enabled. Fallback is disabled (default). Enable fixed secondary fallback. Enable rotating secondary fallback.
0x00109 Fallback Type Select
3:0
FSMSN
6.1.8 Fallback Trigger Registers The fallback trigger registers are used in conjunction with the fallback type select register and control which H-bus clocks are enabled to trigger a clock fallback event in case of error. The sync reference inputs to DPLL1 and DPLL2 can also trigger a clock fallback event upon detection of an error. Agere Systems Inc. 51
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Table 30. Fallback Trigger Registers Byte Address 0x0010A Name Fallback Trigger, Lower Bit(s) Mnemonic Value 7 6 5 4 3 2 1 0 0x0010B Fallback Trigger, Upper 7 6 5 4 3 2 1 0 S2FEB SCFEB C2FEB C4FEB CMFEB CPFEB CBFEB CAFEB Reserved D2FEB D1FEB N2FEB N1FEB FCFEB FBFEB FAFEB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Disable /SCLKx2 trigger (default). Enable /SCLKx2 trigger. Disable SCLK trigger (default). Enable SCLK trigger. Disable C2 trigger (default). Enable C2 trigger. Disable /C4 trigger (default). Enable /C4 trigger. Disable /C16- trigger (default). Enable /C16- trigger. Disable /C16+ trigger (default). Enable /C16+ trigger. Disable CT_C8_B trigger (default). Enable CT_C8_B trigger. Disable CT_C8_A trigger (default). Enable CT_C8_A trigger. NOP (default). Disable DPLL2 sync trigger (default). Enable DPLL2 sync trigger. Disable DPLL1 sync trigger (default). Enable DPLL1 sync trigger. Disable CT_NETREF2 trigger (default). Enable CT_NETREF2 trigger. Disable CT_NETREF1 trigger (default). Enable CT_NETREF1 trigger. Disable /FR_COMP trigger (default). Enable /FR_COMP trigger. Disable /CT_FRAME_B trigger (default). Enable /CT_FRAME_B trigger. Disable /CT_FRAME_A trigger (default). Enable /CT_FRAME_A trigger.
6.1.9 Watchdog Select, C8, and NETREF Registers The watchdog select, C8 register controls the watchdog circuits to monitor the proper frequency for the CT_C8_A and CT_C8_B signals. These signals can take on two values, including 8.192 MHz (ECTF mode) and 4.096 MHz (MC1 mode). The watchdog select, NETREF register controls the watchdog circuits to monitor the proper frequency for the CT_NETREF1 and CT_NETREF2 signals. These signals can take on three values depending on system-level clocking architecture, including 8 kHz (frame reference), 1.544 MHz (T1 bit clock), and 2.048 MHz (E1 bit clock).
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Table 31. Watchdog Select, C8, NETREF Registers Byte Address 0x0010C Name Watchdog Select, C8 Bit(s) Mnemonic 7:4 3:0 0x0010D Watchdog Select, NETREF 7:4 CBWSN CAWSN N2WSN Value 0000 0001 0000 0001 0000 0001 0010 0000 0001 0010 Function CT_C8_B watchdog at 8.192 MHz (default). CT_C8_B watchdog at 4.096 MHz MC1mode. CT_C8_A watchdog at 8.192 MHz (default). CT_C8_A watchdog at 4.096 MHz MC1mode. CT_NETREF2 watchdog at 8 kHz (default). CT_NETREF2 watchdog at 1.544 MHz. CT_NETREF2 watchdog at 2.048 MHz. CT_NETREF1 watchdog at 8 kHz (default). CT_NETREF1 watchdog at 1.544 MHz. CT_NETREF1 watchdog at 2.048 MHz.
3:0
N1WSN
6.1.10 Watchdog EN Register The watchdog EN registers are used to enable/disable watchdogs on the individual H-bus clocks and the watchdogs on the sync inputs of DPLL1 and DPLL2. Table 32. Watchdog EN Registers Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 S2WEB SCWEB C2WEB C4WEB CMWEB CPWEB CBWEB CAWEB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Disable /SCLKx2 watchdog (default). Enable /SCLKx2 watchdog. Disable SCLK watchdog (default). Enable SCLK watchdog. Disable C2 watchdog (default). Enable C2 watchdog. Disable/C4 watchdog (default). Enable/C4 watchdog. Disable/C16- watchdog (default). Enable/C16- watchdog. Disable/C16+ watchdog (default). Enable/C16+ watchdog. Disable CT_C8_B watchdog (default). Enable CT_C8_B watchdog. Disable CT_C8_A watchdog (default). Enable CT_C8_A watchdog.
0x0010E Watchdog EN, Lower
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6 Operating Control and Status (continued)
Table 32. Watchdog EN Registers (continued) Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 FSWEB D2WEB D1WEB N2WEB N1WEB FCWEB FBWEB FAWEB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Disable FAILSAFE ref watchdog (default). Enable FAILSAFE ref watchdog. Disable DPLL2 sync watchdog (default). Enable DPLL2 sync watchdog. Disable DPLL1 sync watchdog (default). Enable DPLL1 sync watchdog. Disable CT_NETREF2 watchdog (default). Enable CT_NETREF2 watchdog. Disable CT_NETREF1 watchdog (default). Enable CT_NETREF1 watchdog. Disable /FR_COMP watchdog (default). Enable /FR_COMP watchdog. Disable /CT_FRAME_B watchdog (default). Enable /CT_FRAME_B watchdog. Disable /CT_FRAME_A watchdog (default). Enable /CT_FRAME_A watchdog.
0x0010F Watchdog EN, Upper
6.1.11 Failsafe Control Registers Table 33. Failsafe Control Register Byte Address 0x00114 Name Failsafe Control Bit(s) Mnemonic 7:0 FSCSR Value Function
0000 0000 NOP (default). 0000 0001 Return from failsafe to nonfallback condition. 0000 0010 Return from failsafe to fallback condition. 0000 0000 Failsafe disabled. 0000 0001 Failsafe enabled. 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 Failsafe watchdog highest sensitivity. Failsafe watchdog + 30.5 ns. Failsafe watchdog + 121.0 ns. Failsafe watchdog + 244.0 ns. Failsafe watchdog + 488.0 ns.
0x00115 0x00116
Failsafe Enable Failsafe Sensitivity
7:0 7:0
FSEER FSSSR
0x00118 0x00119 0x0011A
OOL Threshold Low OOL Threshold High OOL Monitor
7:0 7:0 7:0
OLLLR OLHLR OOLER
LLLL LLLL Failsafe threshold value, low byte. LLLL LLLL Failsafe threshold value, high byte. 0000 0000 Monitor direct APLL1 lock detect at PLOCK. 0000 0001 Monitor user threshold lock detect at PLOCK.
The failsafe control register controls a return from the failsafe state. Writes to the failsafe control register trigger the corresponding action, and the set bit(s) are automatically cleared. From the failsafe state, the user can return to either the primary or secondary clock register sets. For more on failsafe, please see Section 7.7.2 on page 88.
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6 Operating Control and Status (continued)
The failsafe enable register controls the enable/disable of failsafe operation. For more on failsafe operation, please see Section 7.7.2 on page 88. The failsafe sensitivity register allows the failsafe watchdog timer to be desensitized by either 1, 4, 8, or 16 watchdog sample clock periods. The OOL threshold registers allow for programmable threshold times which indicate the APLL1 out-of-lock. Resolution for the threshold value increments is one 32.768 MHz clock period (30.5 ns). The register contains [count - 1], a value of 0x0000 yields a 30.5 ns threshold. A value of 0xFFFF yields a 1.99 ms threshold. For more on OOL operation, please see Section 7.7.2 on page 88. The OOL monitor register allows the user to monitor either the raw APLL1 out-of-lock status, OR the status flag that indicates that the APLL1 has been out-of-lock for more than the threshold defined in the OOL threshold registers. 6.1.12 External Buffers--Descriptor Table Base Address Table 34. Extended Buffers Base Addresses Byte Address 0x00110 0x00111 0x00112 0x00113 Name Base Address Byte 0 Base Address Byte 1 Base Address Byte 2 Base Address Byte 3 Bit(s) 7:0 7:0 7:0 7:0 Mnemonic NA NA NA NA Value Function
LLLL LLLL 32-bit base address value for external buffers descriptor table*. LLLL LLLL 32-bit base address value for external buffers descriptor table*. LLLL LLLL 32-bit base address value for external buffers descriptor table*. LLLL LLLL 32-bit base address value for external buffers descriptor table*.
* The external buffers descriptor table base address is only relevant if the T8110 interfaces to the PCI bus. If the selected T8110 interface is to the microprocessor bus, this register is reserved. For more details, refer to Section 14.2.3.4 on page 160.
6.2 Error and Status Registers
Status 7, 6, and 3--0 registers are writable by the user for clearing specific error bits. Writing a 1 to any of the bits of these registers will clear the corresponding error bit. The remaining error and status registers are read-only. Table 35. Error and Status Register Map DWORD Address (20 bits) 0x00120 0x00124 0x00128 0x0012C Register Byte 3 Status 3, latched clock errors, upper Status 7, system errors, upper Device ID, upper Reserved Byte 2 Status 2, latched clock errors, lower Status 6, system errors, lower Device ID, lower Reserved Byte 1 Status 1, transient clock errors, upper Status 5 PLL and switching status Reserved Status 9, virtual channel status Byte 0 Status 0, transient clock errors, lower Status 4 fallback and failsafe status Version ID Status 8, PCI target queue status
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6 Operating Control and Status (continued)
6.2.1 Clock Errors 6.2.1.1 Transient Clock Errors Registers The transient clock error registers are used in conjunction with the watchdog EN registers and indicate error status for H-bus clocks and DPLL1/DPLL2 sync inputs whose watchdogs are enabled. The transient indicators are dynamic in nature; if a clock is in error only for a short time and then recovers, the error indication is deasserted when the clock recovers. Additionally, an APLL1 out-of-lock indicator is provided, and used in conjunction with the failsafe clocking mode. For more details, please see Section 7.7.1 on page 82 and Section 7.7.2 on page 88. Table 36. Clock Error Registers Byte Address 0x00120 Name Status 0, Transient Clock Errors, Lower Bit(s) Mnemonic 7 6 5 4 3 2 1 0 0x00121 Status 1, Transient Clock Errors, Upper 7 6 5 4 3 2 1 0 S2TOB SCTOB C2TOB C4TOB CMTOB CPTOB CBTOB CATOB FSTOB D2TOB D1TOB N2TOB N1TOB FCTOB FBTOB FATOB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function /SCLKx2 no error (default). /SCLKx2 error. SCLK no error (default). SCLK error. C2 no error (default). C2 error. /C4 no error (default). /C4 error. /C16- no error (default). /C16- error. /C16+ no error (default). /C16+ error. CT_C8_B no error (default). CT_C8_B error. CT_C8_A no error (default). CT_C8_A error. Failsafe indicator: APLL1 reference no error. APLL1 reference error. DPLL2 sync no error (default). DPLL2 sync error. DPLL1 sync no error (default). DPLL1 sync error. CT_NETREF2 no error (default). CT_NETREF2 error. CT_NETREF1 no error (default). CT_NETREF1 error. /FR_COMP no error (default). /FR_COMP error. /CT_FRAME_B no error (default). /CT_FRAME_B error. /CT_FRAME_A no error (default). /CT_FRAME_A error.
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6.2.1.2 Latched Clock Error Register The latched clock error registers capture transient clock errors. The latched indicators capture and hold any transient error status and are used by the clock fallback logic. For more details, see Section 7.7 on page 82, and Section 12 on page 113 for more details. Table 37. Latched Clock Error Registers Byte Address Name Bit(s) 7 6 5 4 3 2 1 0 0x00123 Status 3, Latched Clock Errors, Upper 7 6 5 4 3 2 1 0 Mnemonic Value S2LOB SCLOB C2LOB C4LOB CMLOB CPLOB CBLOB CALOB FSLOB D2LOB D1LOB N2LOB N1LOB FCLOB FBLOB FALOB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function /SCLKx2 no error (default). /SCLKx2 error. SCLK no error (default). SCLK error. C2 no error (default). C2 error. /C4 no error (default). /C4 error. /C16- no error (default). /C16- error. /C16+ no error (default). /C16+ error. CT_C8_B no error (default). CT_C8_B error. CT_C8_A no error (default). CT_C8_A error. Failsafe indicator: APLL1 reference no error. APLL1 reference error. DPLL2 sync no error (default). DPLL2 sync error. DPLL1 sync no error (default). DPLL1 sync error. CT_NETREF2 no error (default). CT_NETREF2 error. CT_NETREF1 no error (default). CT_NETREF1 error. /FR_COMP no error (default). /FR_COMP error. /CT_FRAME_B no error (default). /CT_FRAME_B error. /CT_FRAME_A no error (default). /CT_FRAME_A error.
0x00122 Status 2, Latched Clock Errors, Lower
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6 Operating Control and Status (continued)
6.2.2 System Status 6.2.3 Clock Fallback Status Register The upper nibble provides status indicators for clock fallback. FBFOB indicates whether the circuit is in a clock fallback state. FBSOP indicates which of five possible states the circuit is in; see Section 7.7.1 on page 82 for more details. The lower nibble provides status indicators related to the X and Y clock register set active/inactive assignments. XYSOB indicates which of the clock register sets is active. The remaining bits indicate a pending status for GO_CLOCKS, CLEAR_FALLBACK, and FORCE_FALLBACK commands issued (via the fallback control register, 0x00108), which are waiting for a frame sync.
.
Table 38. Fallback and Failsafe Status Register Byte Address Register Name Bit(s) Mnemonic Value 7 6:4 FBFOB FBSOP 0 1 111 000 001 010 011 100 101 0 1 0 1 0 1 0 1 Function Indicates not in fallback/failsafe state (default). Indicates fallback/failsafe state. Fallback state = INITIAL (default). Fallback state = PRIMARY. Fallback state = TO_PRIMARY. Fallback state = SECONDARY. Fallback state = TO_SECONDARY. Failsafe state = FS_1. Failsafe state = FS_2. Clock register Y set is active, X is inactive. Clock register X set is active, Y is inactive. No GO_CLOCKS pending (default). GO_CLOCKS pending, waiting for frame. No CLEAR_FALLBACK pending (default). CLEAR_FALLBACK pending, waiting for frame. No FORCE_FALLBACK pending (default). FORCE_FALLBACK pending, waiting for frame.
0x00124 Status 4, Clock Fallback Status
3 2 1 0
XYSOB GOPOB CFPOB FFPOB
6.2.4 PLL and Switching Status Register The upper 6 bits provide APLL1, DPLL1, and DPLL2 lock status. For more details, see Section 7 on page 62. The lower 2 bits provide memory status as follows: CMROB is an indicator for the connection memory actively resetting; see Section 14.2.1.1 on page 146. DMPOB indicates the active data page used for double-buffered standard switching; see Section 14.2.1.2 on page 148.
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6 Operating Control and Status (continued)
Table 39. PLL and Switching Status Register Byte Address Register Name Bit(s) Mnemonic Value 7 6 5:4 A1LOB OOLOB D1LOP 0 1 0 1 00 01 10 11 00 01 10 11 0 1 0 1 APLL1 in-lock. APLL1 out-of-lock. Out-of-lock indicator inactive. Out-of-lock indicator active. DPLL1 in-lock (default). DPLL1 out-of-lock, slow correction. DPLL1 out-of-lock, fast correction. Invalid. DPLL2 in-lock (default). DPLL2 out-of-lock, slow correction. DPLL2 out-of-lock, fast correction. Invalid. Connection memory not resetting (default). Connection memory reset loop is active. Active page = data memory page 1. Active page = date memory page 2. Function
0x00125 Status 5, PLL and Switching Status
3:2
D2LOP
1 0
CMROB DPGOB
6.2.5 System Errors Register Table 40. System Errors Registers Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 PMFOB PMLOB PMEOB PMWOB PMOOB PMIOB VCOOB NQOOB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function No error. PCI master, PCI bus fatal error. No error. PCI master, external buffer LOCK error. No error. PCI master, external buffer STALL error. No warning. PCI master, external buffer STALL warning. No warning. PCI master, external buffer overwrite warning. No warning. PCI master, external buffer INITIAL warning. No warning. VC memory, scratchpad overflow warning. No warning. NOTIFY_QUEUE, overflow warning.
0x00126 Status 6, System Errors, Lower
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6 Operating Control and Status (continued)
Table 40. System Errors Registers (continued) Byte Address Register Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 CFSOB CFBOB MBTOB VCTOB DMTOB MBPOB VCPOB DMPOB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function No error. Clock failsafe indicator. No error. Clock fallback indicator. No time-out. PCI target, minibridge discard timer expired. No time-out. PCI target, VC memory discard timer expired. No time-out. PCI target, data memory discard timer expired. No error. PCI target, minibridge protocol error. No error. PCI target, VC memory protocol error. No error. PCI target, data memory protocol error.
0x00127 Status 7, System Errors, Upper
6.2.6 Device Identification Registers These registers identify the device type and revision status, T8110 revision n. Table 41. Device Identification Registers Byte Address Name Bit(s) Mnemonic 7:0 7:0 7:0 VEROR IDLOR IDHOR Value Function
0x00128 Version ID 0x0012A Device ID, Lower 0x0012B Device ID, Upper
0000 0001 Revision status (value shown = REV1). 0001 0000 Device ID low status 0x10. 1000 0001 Device ID high status 0x81.
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6 Operating Control and Status (continued)
6.2.7 Miscellaneous Status The status 8 register provides the status flags which indicate that there is currently a posted write or a delayed read enqueued, one flag for each access region minibridge, virtual channel memory, and data memory. Please refer to Sections 4.1.4, 4.1.4.1, and 4.1.5.1 for more details. The status 9 register provides the current state of the virtual channel switching (START or PAUSE), and the status of any pending start/pause commands that are waiting for the next frame. Please refer to Section 14.2.3. for more details. Table 42. Miscellaneous Status Registers Byte Address Name Bit(s) Mnemonic 7:3 2 1 0 0x0012D Status 9 7:6 5 4 3:0 Reserved MBSOB VCSOB DMSOB Reserved VPPOB VSPOB VCEON Value 0000 0 0 1 0 1 0 1 00 0 1 0 1 0000 0001 NOP. Minibridge PCI target queue is empty. Minibridge PCI target queue is full. VC memory PCI target queue is empty. VC memory PCI target queue is full. Data memory PCI target queue is empty. data memory PCI target queue is full. NOP. No PAUSE command pending. PAUSE is pending (waiting for frame). No START command pending. START is pending (waiting for frame). PAUSE virtual channel switching (disabled). START virtual channel switching (enabled). Function
0x0012C Status 8
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7 Clock Architecture
WATCHDOGS
/CT_FRAME_A /CT_FRAME_B /FR_COMP LREF[4:7] PROGRAMMABLE INVERSION LREF[0:7] CT_NETREF1 CT_NETREF2 CT_C8_A CT_C8_B
BIT SLIDER CONTROLS FRAME SEL 4 SAMPLED FRAME SYNC
WATCHDOG
PHASE ALIGNMENT
2.048 MHz 4.096 MHz 8.192 MHz 16.364 MHz FRAME 32.768 MHz (INTERNAL) FRAME MEMORIES
DPLL1 SOURCE AND RATE
CLOCK SELECT 8 RESOURCE DIVIDE-BY-n DIVIDE REGISTER MAIN DIVIDE-BY-n DIVIDE REGISTER
2 OR 4 MHz DPLL1
INTERNAL CLOCK GENERATION
APLL1 65.536 MHz
65.536 MHz APLL1 BYPASS
WATCHDOGS
MVIP (2 CLOCKS) H-MVIP (4 CLOCKS) SC-BUS (2 CLOCKS) SCSA (2 CLOCKS)
CLK SEL
PROG. INVERSION
FAIL SAFE CLOCK SOURCE SELECT MULT BY 2
WATCHDOG
FRAME
TO TCLK_OUT MUX DPLL2 1, 5, 3, 6, or 12 MHz APLL2 49.408 MHz X4 X8
DIV BY 4
OSC1
DPLL2 SOURCE AND RATE PRI_REF_OUT PRI_REF_IN
APLL2 BYPASS
APLL2 RATE SELECT XTAL2 OUT
OSC2
XTAL1 OUT
XTAL1 IN/ OSC1 IN
XTAL2 IN/ OSC2 IN 5-9432 (F)
Figure 19. T8110 Main Clocking Paths
NR1_SEL_OUT PROGRAMMABLE INVERSION CT_NETREF2 NETREF1 SEL DIV BY 8 8 NR1 SOURCE SELECT NR2 SOURCE SELECT NETREF2 SEL CT_NETREF1 PROGRAMMABLE INVERSION NR2_SEL_OUT
NR1_DIV_IN
PROGRAMMABLE INVERSION
NETREF1 DIVIDE-BY-n NR1 DIV SELECT DIVIDE REGISTER
CT_NETREF1
(FROM XTAL2) (FROM XTAL1)
LREF[0:7]
NR2 DIV SELECT
NETREF2 DIVIDE-BY-n DIVIDE REGISTER PROGRAMMABLE INVERSION
CT_NETREF2
NR2_DIV_IN
5-9433 (F)
Figure 20. T8110 NETREF Paths
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7 Clock Architecture (continued)
7.1 Clock Input Control Registers
The following registers control the T8110 main clocking paths and NETREF paths. Table 43. Clock Input Control Register Map DWORD Address (20 bits) 0x00200 0x00204 0x00208 0x0020C 0x00210 0x00214 Register Byte 3 APLL1 rate APLL2 rate DPLL1 rate DPLL2 rate Reserved Reserved Byte 2 APLL1 input selector Reserved DPLL1 input selector DPLL2 input selector NETREF1 LREF select NETREF2 LREF select Byte 1 Main divider Resource divider Reserved Reserved NETREF1 divider NETREF2 divider Byte 0 Main input selector Main inversion select LREF input select LREF inversion select NETREF1 input selector NETREF2 input selector
7.1.1 Main Input Selector Register The main input selector register controls clock and frame input selection. Table 44. Main Input Selector Register Byte Address 0x00200 Name Main Input Selector Bit(s) 7:0 Mnemonic CKMSR Value 0000 0000 0001 0001 0001 0010 0010 0001 0010 0010 0100 0001 0100 0010 0100 0100 0100 1000 1000 0000 1000 0001 1000 0010 1000 0100 1000 1000 Function Select oscillator/crystal (default). Select NETREF1. Select NETREF2. Select LREF[0:7] individually. Select LREF[0:3, 4:7] paired. Select H-bus A-clocks. Select H-bus B-clocks. Select MC1 R-clocks. Select MC1 L-clocks. Select MVIP clocks (C2 bit clock)*. Select MVIP clocks (/C4 bit clock). Select H-MVIP clocks (/C16 bit clock). Select SC-bus clocks 2 MHz. Select SC-bus clocks 4/8 MHz.
* C2 is allowed as the bit clock input.
Choices include the following: Oscillator/crystal clock = XTAL1_IN (16.384 MHz), no frame NETREF1 clock = CT_NETREF1 (8 kHz, 1.544 MHz, or 2.048 MHz), no frame NETREF2 clock = CT_NETREF2 (8 kHz, 1.544 MHz, or 2.048 MHz), no frame LREF individual clock = one of LREF[0:7]*, no frame LREF paired clock = one of LREF[0:3], frame = one of LREF[4:7]* H-bus A-clocks clock = CT_C8_A (8.192 MHz), frame = /CT_FRAME_A (8 kHz)
* Selection of which LREF is controlled at register 0x00208. Selection of LREF polarity is controlled at register 0x0020C.
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7 Clock Architecture (continued)
H-bus B-clocks clock = CT_C8_B (8.192 MHz), frame = /CT_FRAME_B (8 kHz) MC1 R-clocks clock = inverted CT_C8_A (4.096 MHz), frame = /CT_FRAME_A (8 kHz) MC1 L-clocks clock = inverted CT_C8_B (4.096 MHz), frame = /CT_FRAME_B (8 kHz)
MVIP clocks clock = /C4 (4.096 MHz), frame = /FR_COMP (8 kHz) MVIP clocks* clock = C2 (2.048 MHz), frame = /FR_COMP (8 kHz)
H-MVIP clocks clock = /C16 (16.384 MHz), frame = /FR_COMP (8 kHz) SC-BUS 2 MHz clock = /SCLKx2, frame = /FR_COMP (8 kHz) SC-BUS 4/8 MHz clock = SCLK, frame = /FR_COMP (8 kHz)
* C2 is allowed as the bit clock input.
7.1.2 Main Divider Register The main divider register contains [divider value - 1]. A value of 0x00 yields a divide-by-1 function. A value of 0xFF yields a divide-by-256 function. Table 45. Main Divider Register Byte Address Name Bit(s) Mnemonic 7:0 CKMDR Value LLLL LLLL Function Divider value, {0x00 to 0xFF} = {div1 to div256}, respectively.
0x00201 Main Divider
7.1.3 Analog PLL1 (APLL1) Input Selector Register The APLL1 input selector register controls APLL1 reference input selection. The choices include the following:
n APLL1 reference clock = oscillator/4 (4.096 MHz) n APLL1 reference clock = output of the main divider (4.096 MHz or 2.048 MHz) n APLL1 reference clock = output of the resource divider (4.096 MHz or 2.048 MHz) n APLL1 reference clock = output of DPLL1 (4.096 MHz or 2.048 MHz) n APLL1 reference clock = input from signal PRI_REF_IN (4.096 MHz or 2.048 MHz)
Table 46. APLL1 Input Selector Register Byte Address Name Bit(s) Mnemonic 7:0 P1ISR Value 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 Function Select oscillator/4 (default). Select main divider output. Select resource divider output. Select DPLL1 output. Select external input PRI_REF_IN.
0x00202 APLL1 Input Selector
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7 Clock Architecture (continued)
7.1.4 APLL1 Rate Register The APLL1 rate register provides the rate multiplier value to APLL1. When APLL1 reference clock is at 4.096 MHz, the [x16 (multiplied by)] value must be selected. When APLL1 reference clock is at 2.048 MHz, the [x32 (multiplied by)] value must be selected. A [x1 (multiplied by)] value is provided in order to bypass APLL1. Table 47. APLL1 Rate Register Byte Address Name Bit(s) Mnemonic 7:0 P1RSR Value 0000 0000 0000 0001 0001 xxxx Function Times 16 (default). Times 32. Times 1 BYPASS (lower nibble is don't care).
0x00203 APLL1 Rate
7.1.5 Main Inversion Select Register The main inversion select register controls programmable inversions at various points within the T8110 main clocking paths and NETREF paths. Internal points allowed for programmable inversion include the following:
n Main clock selection CLK SEL MUX output; see Figure 19 on page 62. n NETREF2 divider output; see Figure 20 on page 62. n NETREF2 selection MUX output n NETREF1 divider output n NETREF1 selection MUX output
Table 48. Main Inversion Select Register Byte Address Name Bit(s) Mnemonic 7:5 4 3 2 1 0 Reserved ICMSB N2DSB N2SSB N1DSB N1SSB Value 000 0 1 0 1 0 1 0 1 0 1 NOP (default). Don't invert main clock selection (default). Invert main clock selection. Don't invert NETREF2 divider output (default). Invert NETREF2 divider output. Don't invert NETREF2 selection (default). Invert NETREF2 selection. Don't invert NETREF1 divider output (default). Invert NETREF1 divider output. Don't invert NETREF1 selection (default). Invert NETREF1 selection. Function
0x00204 Main Inversion Select
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7 Clock Architecture (continued)
7.1.6 Resource Divider Register The resource divider register contains [divider value - 1]. A value of 0x00 yields a divide-by-1 function. A value of 0xFF yields a divide-by-256 function. Table 49. Resource Divider Register Byte Address 0x00205 Name Resource Divider Bit(s) Mnemonic 7:0 CKRDR Value Function
LLLL LLLL Divider value, {0x00 to 0xFF} = {div1 to div256}, respectively.
7.1.7 Analog PLL2 (APLL2) Rate Register The APLL2 rate register provides the rate multiplier value to APLL2. When the APLL2 reference clock is at 12.352 MHz, the (times 4) value must be selected. When the APLL2 reference clock is at 6.176 MHz, the (times 8) value must be selected. A (times 1) value is provided in order to bypass APLL2. Table 50. APLL2 Rate Register Byte Address Name Bit(s) Mnemonic 7:0 P2RSR Value 0000 0000 0000 0001 0001 xxxx Function Times 4 (default). Times 8. Times 1 BYPASS (lower nibble is don't care).
0x00207 APLL2 Rate
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7 Clock Architecture (continued)
7.1.8 LREF Input Select Registers The LREF input select register is used in conjunction with the main input selector (0x00200) and provides the selection control among the eight LREF inputs when the main selection is set for either individual or paired LREFs. The LREF inversion select register allows programmable inversion for each LREF input. Please refer to Figure 19 on page 62 for further details. Table 51. LREF Input/Inversion Select Registers Byte Address Name Bit(s) Mnemonic 7:0 LRISR Value 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 0001 0001 0010 0010 0100 0100 1000 1000 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Select LREF0 (default). Select LREF0. Select LREF1. Select LREF2. Select LREF3. Select LREF4. Select LREF5. Select LREF6. Select LREF7. Select paired, clock = LREF0, frame = LREF4. Select paired, clock = LREF1, frame = LREF5. Select paired, clock = LREF2, frame = LREF6. Select paired, clock = LREF3, frame = LREF7. Don't invert LREF7 (default). Invert LREF7. Don't invert LREF6 (default). Invert LREF6. Don't invert LREF5 (default). Invert LREF5. Don't invert LREF4 (default). Invert LREF4. Don't invert LREF3 (default). Invert LREF3. Don't invert LREF2 (default). Invert LREF2. Don't invert LREF1 (default). Invert LREF1. Don't invert LREF0 (default). Invert LREF0.
0x00208 LREF Input Select
0x0020C LREF Inversion Select
7 6 5 4 3 2 1 0
IR7SB IR6SB IR5SB IR4SB IR3SB IR2SB IR1SB IR0SB
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7 Clock Architecture (continued)
7.1.9 DPLL1 Input Selector The DPLL1 input selector selects one of three sources for DPLL1 synchronization input (see Section 7.4.2 on page 78), including the following:
n Main clock selection CLK SEL MUX output n Main divider output n Resource divider output
7.1.9.1 DPLL1 Rate Register The DPLL1 rate register controls the DPLL1 output frequency. Table 52. DPLL1 Input Selector Registers Byte Address Name Bit(s) Mnemonic 7:0 D1ISR Value 0000 0000 0000 0001 0000 0010 0000 0000 0000 0001 Function Main selector (default). Main divider. Resource divider. DPLL1 output at 4.096 MHz (default). DPLL1 output at 2.048 MHz.
0x0020A DPLL1 Input Selector
0x0020B DPLL1 Rate
7:0
D1RSR
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7 Clock Architecture (continued)
7.1.10 DPLL2 Input Selector The DPLL2 input selector selects one of five sources for DPLL2 synchronization input (see Section 7.5.1 on page 81), including the following:
n Main clock selection CLK SEL MUX output n Main divider output n Resource divider output n Internal frame n External input via PRI_REF_IN signal
7.1.10.1 DPLL2 Rate Register The DPLL2 rate register controls the DPLL2 output frequency. Table 53. DPLL2 Register Byte Address Name Bit(s) Mnemonic 7:0 D2ISR Value 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 Function Main selector (default). Main divider. Resource divider. T8110 internally generated frame. External input PRI_REF_IN. DPLL2 output DPLL2 output DPLL2 output DPLL2 output DPLL2 output off (default). at 1.544 MHz. at 3.088 MHz. at 6.176 MHz. at 12.352 MHz.
0x0020E DPLL2 Input Selector
0x0020F DPLL2 Rate
7:0
D2RSR
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7 Clock Architecture (continued)
7.1.11 NETREF1 Registers The NETREF1 input selector, NETREF1 divider, and NETREF1 LREF select registers control the signal paths used to generate CT_NETREF1 (see Figure 20 on page 62). Table 54. NETREF1 Registers Byte Address 0x00210 Name NETREF1 Input Selector Bit(s) Mnemonic 7:4 3:0 N1DSN N1ISN Value 0000 0001 0000 0001 0010 0100 1000 Function Divider input = selector output (default). Divider input = external input NR1_DIV_IN. Oscillator/XTAL1-div-8, 2.048 MHz (default). Oscillator/XTAL1, 16.384 MHz. CT_NETREF2 input. LREF input*. Oscillator/XTAL2, 6.176 MHz, or 12.352 MHz.
0x00211 0x00212
NETREF1 Divider NETREF1 LREF Select
7:0 7:0
NR1DR N1LSR
LLLL LLLL Divider value, {0x00 to 0xFF} = {div1 to div256}, respectively. 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 Select LREF0 (default). Select LREF0. Select LREF1. Select LREF2. Select LREF3. Select LREF4. Select LREF5. Select LREF6. Select LREF7.
* Selection of which LREF is controlled at register 0x00212.
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7 Clock Architecture (continued)
7.1.12 NETREF2 Registers The NETREF2 input selector, NETREF2 divider, and NETREF2 LREF select registers control the signal paths used to generate CT_NETREF2 (see Figure 20 on page 62). Table 55. NETREF2 Registers Byte Address Name Bit(s) Mnemonic 7:4 3:0 N2DSN N2ISN Value 0000 0001 0000 0001 0010 0100 1000 Function Divider input = selector output (default). Divider input = external input NR1_DIV_IN. Oscillator/XTAL1-div-8, 2.048 MHz (default). Oscillator/XTAL1, 16.384 MHz. CT_NETREF1 input. LREF input*. Oscillator/XTAL2, 6.176 MHz, or 12.352 MHz.
0x00214 NETREF2 Input Selector
0x00215 NETREF2 Divider 0x00216 NETREF2 LREF Select
7:0 7:0
NR2DR N2LSR
LLLL LLLL Divider value, {0x00 to 0xFF} = {div1 to div256}, respectively. 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 Select LREF0 (default). Select LREF0. Select LREF1. Select LREF2. Select LREF3. Select LREF4. Select LREF5. Select LREF6. Select LREF7.
* Selection of which LREF is controlled at register 0x00216.
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7 Clock Architecture (continued)
7.2 Clock Output Control Registers
The registers listed below control output enable and rate selection of the T8110 clock path outputs. Table 56. Clock Output Control Register Map DWORD Address (20 bits) 0x00220 0x00224 0x00228 Register Byte 3 C8 output rate SCLK output rate L_SC3 select Byte 2 /FR_COMP width TCLK select L_SC2 select Byte 1 NETREF output enables Reserved L_SC1 select Byte 0 Master output enables CCLK output enables L_SC0 select
7.2.1 Master Output Enables Register The master output enables register controls the output enables for H-bus and compatibility clocks (CCLK) for T8110 clock mastering. A-clocks refers to the combination of CT_C8_A bit clock and /CT_FRAME_A frame reference. B-clocks refers to the CT_C8_B bit clock and /CT_FRAME_B frame reference. These programmable enables are used in conjunction with master enable register 0x00103, H-bus clock enables, HCKEB. The NETREF output enables register controls the output enables for CT_NETREF1 and CT_NETREF2. These programmable enables are used in conjunction with master enable register 0x00103, H-bus clock enables, HCKEB. The CCLK output enables register is used in conjunction with register 0x00220 and controls the output enables for various groupings of compatibility clocks, including the following:
n H-MVIP bit clock only(/C16) n MVIP clocks (/C4, C2) n H-MVIP clocks (/C16, /C4, C2) n SC-bus clocks (SCLK, /SCLKx2) n /FR_COMP compatibility frame reference
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7 Clock Architecture (continued)
Table 57. Master Output Enables Registers Byte Address 0x00220 Name Master Output Enables Bit(s) Mnemonic 7:4 ABOEN Value 0000 0001 0010 0011 0000 0001 0010 0000 0001 0000 0001 0000 0001 0000 0001 0010 0011 0100 Function Disable A and B clock outputs (default). Enable A clock outputs only. Enable B clock outputs only. Enable both A and B clock outputs. Disable compatibility (C clock) outputs (default). Enable C clocks individually*. Enable all C clocks. CT_NETREF2 disabled (default). CT_NETREF2 enabled. CT_NETREF1 disabled (default). CT_NETREF1 enabled. /FR_COMP disabled (default). /FR_COMP enabled. C-clock bit clocks disabled (default). Enable H-MVIP bit clock. Enable MVIP clocks. Enable H-MVIP all clocks. Enable SC-bus clocks.
3:0
CCOEN
0x00221
NETREF Output Enables CCLK Output Enables
7:4 3:0 7:4 3:0
N2OEN N1OEN FRSEN CCSEN
0x00224
* Overall selection includes all C clocks OFF, all C clocks ON, or select individual groups of C clocks to be enabled, in conjunction with register 0x00224.
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7 Clock Architecture (continued)
7.2.2 Clock Output Format Registers The clock output format registers select the pulse width of the /FR_COMP pulse width. The C8 output rate register selects the CT_C8_A and CT_C8_B clock output frequency 8.192 MHz for ECTF (H1x0) mode, or 4.096 MHz for MC1 mode. The SCLK output rate register selects between three SC-Bus clock configurations, including the following:
n SCLK = 2.048 MHz, /SCLKx2 = 4.096 MHz n SCLK = 4.096 MHz, /SCLKx2 = 8.192 MHz n SCLK = 8.192 MHz, /SCLKx2 = 8.192 MHz (phase shifted from SCLK)
Table 58. Clock Output Format Registers Byte Address Name Bit(s) Mnemonic 7:0 7:4 3:0 0x00227 SCLK Output Rate 7:0 FRWSR BCRSN ACRSN SCRSR Value Function
0x00222 /FR_COMP Width 0x00223 C8 Output Rate
0000 0000 /FR_COMP width is 122 ns (default). 0000 0001 /FR_COMP width is 244 ns. 0000 0001 0000 0001 CT_C8_B output at 8.192 MHz (default). CT_C8_B output at 4.096 MHz, MC1 mode. CT_C8_A output at 8.192 MHz (default). CT_C8_A output at 4.096 MHz, MC1 mode.
0000 0000 SCLK = 2 MHz, /SCLKx2 = 4 MHz (default). 0000 0001 SCLK = 4 MHz, /SCLKx2 = 8 MHz. 0000 0010 SCLK = 8 MHz, /SCLKx2 = 8 MHz phase shifted.
7.2.3 TCLK and L_SCx Select Registers The TCLK select register controls the selection of various internally generated clocks for output to the TCLK_OUT signal. The L_SCx select registers control the selection of various internally generated clocks for output to the L_SC0, L_SC1, L_SC2, and L_SC3 signals.
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7 Clock Architecture (continued)
Table 59. TCLK Select and L_SCx Select Registers Byte Address 0x00226 Name TCLK Select Bit(s) Mnemonic 7:0 TCOSR Value 0000 0000 0000 0001 0000 0010 0001 0001 0001 0010 0010 0000 0010 0001 0010 0010 0011 0000 0011 0001 0011 0010 0100 0000 0100 0001 0100 0010 0100 0100 0100 1000 0101 0000 0101 0001 0101 0010 0101 0100 0101 1000 1000 0000 1000 0001 1000 0010 1001 0000 1001 0001 1001 0010 0000 0000 0000 0001 0001 0001 0100 0000 0100 0001 0100 0010 0100 0100 0100 1000 0101 0000 0101 0001 0101 0010 0101 0100 0101 1000 1000 0000 1000 0001 1000 0010 1001 0000 1001 0001 1001 0010 Function TCLK output disabled (default). Select OSC1/XTAL1. Select OSC2/XTAL2. Select OSC1/XTAL1 inverted. Select OSC2/XTAL2 inverted. Select DPLL2 output. Select APLL1 output, 65.536 MHz. Select APLL2 output, 49.704 MHz. Select DPLL2 output inverted. Select APLL1 output inverted. Select APLL2 output inverted. Select generated 2.048 MHz. Select generated 4.096 MHz. Select generated 8.192 MHz. Select generated 16.384 MHz. Select generated 32.768 MHz. Select generated 2.048 MHz inverted. Select generated 4.096 MHz inverted. Select generated 8.192 MHz inverted. Select generated 16.384 MHz inverted. select generated 32.768 MHz inverted. Select generated frame. Select generated CT_NETREF1. Select generated CT_NETREF2. Select generated frame inverted. Select generated CT_NETREF1 inverted. Select generated CT_NETREF2 inverted. L_SCx output disabled (default). Select OSC1/XTAL1. Select OSC1/XTAL1 inverted. Select generated 2.048 MHz. Select generated 4.096 MHz. Select generated 8.192 MHz. Select generated 16.384 MHz. Select generated 32.768 MHz. Select generated 2.048 MHz inverted. Select generated 4.096 MHz inverted. Select generated 8.192 MHz inverted. Select generated 16.384 MHz inverted. Select generated 32.768 MHz inverted. Select generated frame. Select generated CT_NETREF1. Select generated CT_NETREF2. Select generated frame inverted. Select generated CT_NETREF1 inverted. Select generated CT_NETREF2 inverted.
0x00228 (0x00229) (0x0022A) (0x0022B)
L_SC0 Select L_SC1 Select L_SC2 Select L_SC3 Select
7:0
LC0SR (LC1SR) (LC2SR) (LC3SR)
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7 Clock Architecture (continued)
7.3 Clock Register Access
The T8110 clock control registers, 0x00200--0x002FF, consist of two identical sets of registers, X and Y. At any given time, only one set is actually controlling the clocking (denoted as the active set), while the other is in a standby state (inactive set). Either set, X or Y, may be the active set, as determined by a state machine that tracks the clock fallback control and status and assigns either set to be active accordingly. For more details, see Section 7.7.1 on page 82. Users may only access one register set at a time. By default, access is allowed to the current inactive set, but access to the active set is allowed via the clock register access select register, 0x00106; see Section 6.1.4 on page 49.
7.4 Clock Circuit Operation--APLL1
APLL1 can accept either a 4.096 MHz or 2.048 MHz reference clock, and perform a corresponding multiplication function to supply a 65.536 MHz operating clock for the T8110. Additionally, APLL1 may be bypassed for circuit diagnostic purposes. Please refer to Figure 19 on page 62. 7.4.1 Main Clock Selection, Bit Clock, and Frame APLL1 clock references are selectable as stand-alone bit clocks, frames, or a pairing of bit clock and frame (see main input selector register, 0x00200). The bit clock output of the main clock selection is available as input to the main divider, resource divider, and DPLL1. Table 60. Bit Clock and Frame Bit Clock CT_NETREF1, CT_NETREF2 NA CT_C8_A CT_C8_B /C16 /C4 C2 SCLK /SCLKx2 LREF[0] LREF[1] LREF[2] LREF[3] LREF[4] LREF[5] LREF[6] LREF[7] Corresponding 8 kHz Frame -- CT_NETREF1, CT_NETREF2 /CT_FRAME_A /CT_FRAME_B /FR_COMP /FR_COMP /FR_COMP /FR_COMP /FR_COMP LREF[4] LREF[5] LREF[6] LREF[7] -- -- -- --

Value(s) 1.544 MHz (T1), 2.048 MHz (E1) 8 kHz 8.192 MHz (ECTF), 4.096 MHz (MC1) 8.192 MHz (ECTF), 4.096 MHz (MC1) 6.384 MHz (H-MVIP) 4.096 MHz (MVIP) 2.048 MHz (MVIP*) 2.048 MHz, 4.096 MHz, 8.192 MHz (SC-bus) 4.096 MHz, 8.192 MHz (SC-bus) System-specific System-specific System-specific System-specific System-specific System-specific System-specific System-specific
* MVIP, /C4 is typically the bit clock. C2 is selectable as the bit clock as well. When LREF pairing is enabled.
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7 Clock Architecture (continued)
7.4.1.1 Watchdog Timers A set of watchdog timers is available for all H1x0, H-MVIP, MVIP, and SC-bus clocks. No watchdogs are available for LREF[7:0] directly; however, the LREF inputs may be monitored indirectly via watchdogs on the DPLL1 and DPLL2 sync inputs, or via the failsafe mechanism; see Section 7.7.2 on page 88. The watchdogs sample the incoming clocks at 32.768 MHz (derived from the XTAL1 crystal) and monitor for loss of signal, as shown below. Table 61. Watchdog Timer Description Watchdog H1x0 clock monitors* Signal, Value CT_C8_A at 8.192 MHz CT_C8_B at 8.192 MHz CT_C8_A at 4.096 MHz CT_C8_B at 4.096 MHz FRAME monitors /CT_FRAME_A /CT_FRAME_B /FR_COMP Description ECTF mode. Checks for CT_C8 rising edge within a 35 ns window of its expected arrival. MC1 mode. Monitors for loss of signal (falling edges). Monitors for 8 kHz frequency. Detects frame overflow (i.e., next frame pulse too late) and frame underflow (i.e., next frame pulse too early).
NETREF monitors*
CT_NETREF1 at 1.544 MHz NETREF is T1 bit clock. Monitors for loss of signal CT_NETREF2 at 1.544 MHz (rising or falling edges). CT_NETREF1 at 2.048 MHz NETREF is E1 bit clock. Monitors for loss of signal CT_NETREF2 at 2.048 MHz (rising or falling edges). CT_NETREF1 at 8 kHz CT_NETREF2 at 8 kHz NETREF is 8 kHz frame reference. Monitors for 8 kHz frequency. Detects frame overflow (i.e., next frame pulse too late) and frame underflow (i.e., next frame pulse too early). Gross loss-of-signal detector--clocks are sampled and normalized to 1.024 MHz. It can take up to 976 ns for these watchdog timers to detect loss of a compatibility clock.
Compatibility clock monitors
/C16 at 16.384 MHz /C4 at 4.096 MHz C2 at 2.048 MHz SCLK, /SCLKx2 at any of their defined values.
DPLL1, DPLL2 sync monitors
Output of MUX selector to the Monitors for 8 kHz frequency. Detects frame overflow SYNC input of each (i.e., next frame pulse too late) and frame underflow DPLL (8 kHz) (i.e., next frame pulse too early).
* User selects frequency at which to monitor the CT_C8 clocks via register 0x0010C, watchdog select, C8. DPLL sync reference is expected to be 8 kHz.
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7 Clock Architecture (continued)
7.4.1.2 Frame Center Sampling Frame center samples are used in order to phase-align the incoming frame reference to the internally generated frame reference; see Section 7.4.5.1 on page 80. The incoming frame reference signal is sampled with a recovered clock (output of the APLL1 feedback divider) to determine the frame center. Frame center sampling is only relevant when the main clock selection is based on a paired bit clock/frame reference, as follows. Table 62. Frame Center Sampling Frame Signal /CT_FRAME_A /CT_FRAME_B /FR_COMP Corresponding Bit Clock CT_C8_A CT_C8_B /C16 (H-MVIP) or /C4 (MVIP) or C2 (MVIP) SCLK or /SCLKx2 (SC-bus) LREF[0] LREF[1] LREF[2] LREF[3] Sample Clock Recovered 8.192 MHz, rising edge. Recovered 8.192 MHz, rising edge. Recovered 4.096 MHz, falling edge.
/FR_COMP LREF[4] LREF[5] LREF[6] LREF[7]
Recovered 2.048 MHz, rising edge. Recovered 2.048 MHz, rising edge. Recovered 2.048 MHz, rising edge. Recovered 2.048 MHz, rising edge. Recovered 2.048 MHz, rising edge.
7.4.2 Main and Resource Dividers Two independently programmable dividers are available to divide down the main clock selection signal. The function ranges from divide-by-1 (bypass) to divide-by-256.
n For binary divider values of 1, 2, 4, 8, 16, 32, 64, 128, and 256, the output is 50% duty cycle. n For a divider value of 193, the output is almost 50% duty cycle (low-level duration is one clock cycle shorter than
high-level duration).
n For all other divider values, the output is a pulse whose width is one full period of the main clock selection signal.
Output of both dividers is available to the DPLL1 and the APLL1 reference selector. The output of the main divider is also available at the PRI_REF_OUT chip output. Both dividers are reset whenever a changeover between X and Y clock register sets is detected; see Section 7.3 on page 76. This allows for immediate loading of the newly activated divider register values.
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7 Clock Architecture (continued)
7.4.3 DPLL1 A digital phase-lock loop is provided to generate a 4.096 MHz or 2.048 MHz reference to APLL1, selectable via register 0x0020B (DPLL1 rate). The DPLL1 operates at 32.768 MHz, derived from the XTAL1 crystal input. The DPLL1 synchronization source is selectable (register 0x0020A, DPLL1 input selector) between the main clock selection signal, the output of the resource divider, or the output of the main divider, and is intended to be presented as an 8 kHz frame reference. DPLL1 is determined to be in-lock or out-of-lock, based on the state of the output clock when an edge transition is detected at the synchronization source. An out-of-lock condition results in a DPLL1 correction, which can either lengthen or shorten its current output clock period by 30.5 ns. 7.4.4 Reference Selector The APLL1 reference clock is selectable between five possible sources via register 0x00202, APLL1 input selector. A 4.096 MHz or 2.048 MHz reference must be provided. The five possible sources are shown below:
n XTAL1 crystal (16.384 MHz) divided-by-4 n Main divider output n Resource divider output n DPLL1 output n PRI_REF_IN external chip input
7.4.5 Internal Clock Generation The main internal functions of T8110 are synchronous to the 65.536 MHz output of APLL1. This clock is further divided to generate 32.768 MHz, 16.384 MHz, and 8 kHz internal reference signals. Additional divide-down values to 8.192 MHz, 4.096 MHz, and 2.048 MHz are generated. These generated clocks are the source for H1x0, H-MVIP, MVIP, and SC-bus clocks when the T8110 is mastering the bus clocks; see Section 7.2 on page 72. These internally generated clocks can either be free-running, or can be aligned to the incoming main selection clock and frame, via a phase alignment circuit (see Section 7.4.5.1).
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7 Clock Architecture (continued)
7.4.5.1 Phase Alignment Phase alignment allows the free-running internally generated clocks to be forced into alignment with the incoming main selection clock and frame, under the following conditions:
n The main selection clock is based on a paired bit clock/frame reference (see Section 7.4.1.2 on page 78), and
the phase alignment circuit is enabled (via register 0x00107, phase alignment select). The incoming frame center is monitored via the frame center samplers (see Section 7.4.1.2 on page 78) and compared to the state of the internally generated frame. The circuit determines whether the frame centers are aligned. If not, three possible actions take place as shown below:
n NOP: no corrections when phase alignment is disabled. n Snap correction: the internally generated clocks and frame immediately snap into alignment with the incoming
frame center.
n Slide correction: the internally generated clocks and frame gradually slide into alignment with the incoming frame
center, at a rate of one 65.536 MHz clock period per frame. The sliding occurs in one direction only and creates frame periods that are 15.25 ns longer than 125 s until the frames are aligned. Please refer to Figure 21.
INCOMING FRAME CENTER INCOMING BIT CLOCK CT_C8_A INCOMING FRAME /CT_FRAME_A INTERNAL CLOCK, 8.192 MHz INTERNAL FRAME
MISALIGNED INTERNAL FRAME CENTER
125 s
INCOMING FRAME CENTER
SNAP ALIGNMENT
REALIGNED INTERNAL FRAME CENTER
5-9414 (F)
A. Phase Alignment--SNAP
125 s INCOMING BIT CLOCK CT_C8_A INCOMING FRAME /CT_FRAME_A 45 ns INTERNAL CLOCK, 8.192 MHz SLIDE ALIGNMENT INTERNAL FRAME MISALIGNED INTERNAL FRAME CENTER MISALIGNED INTERNAL FRAME CENTER MISALIGNED INTERNAL FRAME CENTER REALIGNED INTERNAL FRAME CENTER
5-9415 (F)
125 s
125 s
30 ns
15 ns
SLIDE ALIGNMENT
SLIDE ALIGNMENT
B. Phase Alignment--SLIDE Figure 21. T8110 Phase Alignment, SNAP and SLIDE
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7 Clock Architecture (continued)
7.5 Clock Circuit Operation, APLL2
APLL2 requires either a 6.176 MHz or 12.352 MHz reference clock to produce a 49.408 MHz clock for operating DPLL2. A user-supplied rate multiplier (register 0x00207, APLL2 rate) provides either a times 8 function (when reference clock = 6.176 MHz) or a times 4 function (when reference clock = 12.352 MHz). Additionally, APLL2 may be bypassed for circuit diagnostic purposes (see Figure 19 on page 62). 7.5.1 DPLL2 A second digital phase-lock loop is provided to generate various derivations of T1 operating frequencies, available by selection via the TCLK_OUT output. The possible output frequencies are selectable via register 0x0020F (DPLL2 rate) and include 1.544 MHz, 3.088 MHz, 6.176 MHz, and 12.352 MHz. The DPLL2 input clock operates at 49.408 MHz from the APLL2 output. Synchronization sources for DPLL2 include the same sources provided to DPLL1 (selectable between the main clock selection signal, the output of the resource divider, or the output of the main divider) and two additional sources, including the T8110 internally generated frame signal and the PRI_REF_IN input. These selections are available via register 0x0020E, DPLL2 input selector. DPLL2 is determined to be in-lock or out-of-lock based on the state of its output when an edge transition is detected at the synchronization source. An out-of-lock condition results in a DPLL2 correction, which can either lengthen or shorten its current output clock period by 20.2 ns.
7.6 Clock Circuit Operation, CT_NETREF Generation
The T8110 provides two independently programmable paths to generate CT_NETREF1 and CT_NETREF2, via registers 0x00210--0x00216. Each CT_NETREF is individually enabled with register 0x00221, NETREF output enables. Each path consists of a source selector MUX and a divider circuit (see Figure 20 on page 62). 7.6.1 NETREF Source Select XTAL1 input DIV 8 (2.048 MHz) XTAL1 input (16.384 MHz) XTAL2 input (6.176 MHz or 12.352 MHz) LREF[7:0] CT_NETREFx (the other NETREF--i.e., CT_NETREF1 can be derived from CT_NETREF2, and vise-versa). The output of the source select MUX is made available directly to the NETREF divider, and also to chip output (NR1_SEL_OUT, NR2_SEL_OUT). 7.6.2 NETREF Divider Each NETREF path provides a divider from a divide-by-1 function up to a divide-by-256 function. The clock source for the divider is selectable between the output of the source select MUX or from external chip input (NR1_DIV_IN, NR2_DIV_IN).
n For binary divider values of 1, 2, 4, 8, 16, 32, 64, and 128, output is 50% duty cycle. n For divider values of 256, 193, plus all other nonbinary values, output is a pulse whose width is one-half of a
clock period, asserted during the second half of the divider clock period. The NETREF dividers are reset whenever a changeover between X and Y clock register sets is detected (see Section 7.3 on page 76). This allows for immediate loading of the newly activated divider register values.
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7 Clock Architecture (continued)
7.7 Clock Circuit Operation--Fallback and Failsafe
Fallback is a means to alter the reference source to APLL1 by switching between two clock control register sets upon detection of a fallback event. Failsafe is a feature to provide a safety net for the reference source to APLL1, independent of clock fallback. 7.7.1 Clock Fallback Clock fallback is a means to alter the APLL1 reference clock source upon detection of a fallback event and is controlled by eight registers, 0x00108--0x0010F (refer to Section 6.1.4 on page 49). These registers enable and control the state transitions that determine which of two clock register sets is used to control the APLL1 reference clock source (see Section 7.1 on page 63 through Section 7.3, Table 64 on page 85, and Figure 23 on page 84). 7.7.1.1 Fallback Events Clock fallback (transition from primary to secondary clock sets) can only occur if the fallback mode is enabled (register 0x00109, lower nibble) and a fallback event occurs. When enabled, there are three ways to trigger the fallback event:
n Software, via a FORCE_FALLBACK command. The user sets bit 2 of the fallback control register, 0x00108, creating a software-invoked fallback event.
n Hardware via the fallback trigger enable registers, 0x0010A--0x0010B. User may enable specific watchdog timers and corresponding fallback trigger enable bits. If a watchdog timer indicates a clock error, and its corresponding trigger enable bit is set, a hardware-invoked fallback event is produced.
n Hardware, legacy modes, via the fallback type select register, 0x00109, upper nibble. The legacy modes are included to maintain backwards compatibility with earlier Ambassador devices. User may enable specific watchdog timers, but the fallback trigger enable registers are ignored. Instead, the watchdogs which are allowed to trigger a fallback event are automatically selected based on the state of the main input selector register, 0x00200 (refer to Table 63). If a watchdog timer indicates a clock error, and its corresponding trigger enable is selected via the main input selector, a hardware-invoked fallback event is produced.
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7 Clock Architecture (continued)
Table 63. Legacy Mode Fallback Event Triggers Main Input Selector Function (Register 0x00200) Oscillator/crystal CT_NETREF1 CT_NETREF LREF, individual LREF, paired H-bus, A clocks H-bus, B clocks MC1, R clocks MC1, L clocks Selected Watchdog Triggers (Legacy Modes) None NETREF1 watchdog NETREF2 watchdog None None CT_C8_A and /CT_FRAME_A watchdogs CT_C8_B and /CT_FRAME_B watchdogs None None /C4, C2, and /FR_COMP watchdogs /C16, /C4, C2, and /FR_COMP watchdogs SCLK, /SCLKx2, and /FR_COMP watchdogs
MVIP clocks (/C4 or C2 bit clock)
H-MVIP clocks SC-bus clocks (2 MHz or 4/8 MHz) 7.7.1.2 Fallback Scenarios--Fixed vs. Rotating Secondary
When clock fallback is enabled (register 0x00109, lower nibble), there are two possible scenarios for transitioning between the primary and secondary clock sets. In a fixed secondary scheme, a fallback event switches the active clock set from primary to secondary. When the fallback event is cleared (via user-invoked CLEAR_FALLBACK), the active clock set returns to primary. In a rotating secondary scheme, a fallback event switches the active clock set from primary to secondary. When the fallback event is cleared, the secondary remains as the new active clock set. In effect, the secondary becomes the new primary, and the primary becomes the new secondary. The concepts are illustrated in the figure below.
FALLBACK EVENT
PRIMARY REGISTER SET (X OR Y)
FALLBACK CLEARED
SECONDARY REGISTER SET (X OR Y)
FIXED SECONDARY SCENARIO FALLBACK EVENT FALLBACK CLEARED REGISTER SET X FALLBACK EVENT ROTATING SECONDARY SCENARIO REGISTER SET Y FALLBACK CLEARED
5-9420 (F)
Figure 22. Fallback--Fixed vs. Rotating Secondary
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7 Clock Architecture (continued)
RESET
INITIAL (Y IS THE ACTIVE SET)
USER COMMAND GO_CLOCKS PRIMARY (X IS THE ACTIVE SET)
FALLBACK ENABLED AND FALLBACK EVENT
TO_SECONDARY (Y IS THE ACTIVE SET, ASSERT FALLBACK FLAG)
ROTATING SECONDARY MODE
USER COMMAND CLEAR_FALLBACK FIXED SECONDARY MODE
FALLBACK TYPE ? ROTATING SECONDARY MODE
SECONDARY (Y IS THE ACTIVE SET)
FIXED SECONDARY MODE
FALLBACK TYPE ?
FALLBACK ENABLED AND FALLBACK EVENT TO_PRIMARY (X IS THE ACTIVE SET, ASSERT FALLBACK FLAG)
USER COMMAND CLEAR_FALLBACK
5-9422 (F)
Figure 23. T8110 Clock Fallback States
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7 Clock Architecture (continued)
Table 64. Clock Fallback State Description Clock Fallback State INITIAL Description Y is the active clock register set. Default value provides XTAL1-div-4 reference. X is the active clock register set and controls APLL1 REFCLK. Exit To PRIMARY Exit Condition User issues GO_CLOCKS command (set register 0x00108 bit 0).
PRIMARY
TO_SECONDARY Fallback is enabled and fallback event* occurs. PRIMARY User issues CLEAR_FALLBACK command (set register 0x00108 bit 1) and fallback type = fixed secondary. User issues CLEAR_FALLBACK command (set register 0x00108 bit 1) and fallback type = rotating secondary. Fallback is enabled and fallback event* occurs. User issues CLEAR_FALLBACK command (set register 0x00108 bit 1) and fallback type = fixed secondary. User issues CLEAR_FALLBACK command (set register 0x00108 bit 1) and fallback type = rotating secondary.
TO_SECONDARY Y is the active clock register set and controls APLL1 REFCLK. Fallback flag is asserted.
SECONDARY
SECONDARY
Y is the active clock register set and controls APLL1 REFCLK. X is the active clock register set and controls APLL1 REFCLK. Fallback flag is asserted.
TO_PRIMARY
TO_PRIMARY
SECONDARY
PRIMARY
* Fallback event; refer to Section 7.7.1.1 on page 82. Fixed, rotating secondary; refer to Section 7.7.1.2 on page 83.
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7 Clock Architecture (continued)
7.7.1.3 H-Bus Clock Enable/Disable on Fallback The previous Ambassador devices allowed a fallback mode (A/B fallback) which automatically allowed an H1x0 bus clock master to detect an error in its own output clock and remove itself from the bus, or a clock slave to detect an error on its incoming clock and promote itself to clock master. The H-bus clocks include:
n A clocks: CT_C8_A, /CT_FRAME_A n B clocks: CT_C8_B, /CT_FRAME_B n C clocks: /C16, /C4, C2, SCLK, /SCLKx2, /FR_COMP
Refer to Figure 24 and Table 65. The T8110 allows for this mode of operation in two ways: Register 0x00109(7:4) = 0100: legacy mode, A/B fallback--when this mode is selected, the fallback triggers allowed are predefined based on the main input clock selection, and the state machine which controls H-bus clock enable/disable is activated. Register 0x00109(7:4) = 1001: nonlegacy mode--when this mode is selected, the fallback trigger enable registers determine what triggers a fallback, and the state machine which controls H-bus clock enable/disable is activated.
Diag_ABC
Diag_ABC = Drives A Clocks, B Clocks and C Clocks, no fallback permitted Diag_AB = Drives A Clocks and B Clocks, no fallback permitted C_Only = Drives C Clocks only, no fallback permitted
Diag_AB
The T8110 enters & leaves these states based on Master Output Enable clock register updates, 0x00220
C_Only B_Only = Drives B Clocks, can be promoted to master and drive C clocks in fallbackcondition B_Master = Drives B & C Clocks, all clocks shut off in fallbackcondition B_Error = all clocks shut off, waiting for B clocks to be reprogrammed
Diagnostic/Forced Clocking Fallback Clocking, assumes Fallback enabled in CKS register
Initial
B_Only
B Clocks Fail
B_Error
A Clocks Fail B Clocks Fail Reprogram B Clocks
B_Master
A_Only
A Clocks Fail
A_Error
B Clocks Fail A Clocks Fail Reprogram A Clocks
A_Only = Drives A Clocks, can be promoted to master and drive C clocks in fallbackcondition A_Master = Drives A & C Clocks, all clocks shut off in fallbackcondition A_Error = all clocks shut off, waiting for A clocks to be reprogrammed
A_Master
Figure 24. T8110 H-Bus Clock Enable States
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7 Clock Architecture (continued)
Table 65. H-Bus Clock Enable State Description H-Bus Clock Enable State INITIAL Description Initial condition, waiting for clock output control register programming. T8110 is driving all H-bus clocks (diagnostic mode). T8110 is driving both the H-bus A and B clocks (diagnostic mode). T8110 is driving only the H-bus C clocks. T8110 clock output control registers are programmed to drive A clocks and C clocks (T8110 is an A clock master), or T8110 was supplying a backup A clock and has been promoted to A clock master. Exit To Exit Condition
Any of the User update of the clock output control regisother states ter (0x00220, master output enables). INITIAL INITIAL INITIAL User update of the clock output control register (0x00220, master output enables). User update of the clock output control register (0x00220, master output enables). User update of the clock output control register (0x00220, master output enables).
DIAG_ABC DIAG_AB C_ONLY A_MASTER
A_ERROR A clock error on CT_C8_A or /CT_FRAME_A is detected; disable clock outputs. INITIAL User update of the clock output control register (0x00220, master output enables).
A_ONLY
T8110 clock output control registers A_MASTER A clock error on CT_C8_B or /CT_FRAME_B are programmed to drive A clocks is detected; promote to A clock master. only (T8110 is a B clock slave, and A_ERROR A clock error on CT_C8_A or /CT_FRAME_A supplies a backup A clock). is detected; disable clock outputs. INITIAL User update of the clock output control register (0x00220, master output enables). User update of the clock output control register (0x00220, master output enables).
A_ERROR
T8110 has detected a clock error while driving the A clocks, and has stopped driving any H bus clocks. T8110 clock output control registers are programmed to drive B clocks and C clocks (T8110 is a B clock master), or T8110 was supplying a backup B clock and has been promoted to B clock master.
INITIAL
B_MASTER
B_ERROR A clock error on CT_C8_B or /CT_FRAME_B is detected; disable clock outputs. INITIAL User update of the clock output control register (0x00220, master output enables).
B_ONLY
T8110 clock output control registers B_MASTER A clock error on CT_C8_A or /CT_FRAME_A are programmed to drive B clocks is detected; promote to B clock master. only (T8110 is an A clock slave, and B_ERROR A clock error on CT_C8_B or /CT_FRAME_B supplies a backup B clock). is detected; disable clock outputs. INITIAL User update of the clock output control register (0x00220, master output enables). User update of the clock output control register (0x00220, master output enables).
B_ERROR
T8110 has detected a clock error while driving the B clocks, and has stopped driving any H bus clocks.
INITIAL
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7 Clock Architecture (continued)
7.7.2 Clock Failsafe Clock failsafe provides a safety net for the APLL1 reference clock source and is controlled by three registers, 0x00114--0x00116; see Section 6.1.11 on page 54. A failsafe event overrides the active clock control registers and forces the APLL1 clock selection to be a fixed 4.096 MHz, derived from the XTAL1 crystal, divided by four. Transition into one of the failsafe states is independent of clock fallback (i.e., can enter from any state other than INITIAL). Transitions out of the failsafe states are by user command and allow re-entry into either a nonfallback (primary or secondary) or a fallback (TO_SECONDARY or TO_PRIMARY) state. Refer to Table 66 and Figure 25. 7.7.2.1 Failsafe Events Clock failsafe (transition from either clock register set to a forced XTAL1-div-4 APLL1 reference clock) can only occur if the failsafe mode is enabled (register 0x00115, lower nibble), and a failsafe event occurs. A failsafe event is triggered by a watchdog error on the APLL1 reference clock (i.e., loss-of-reference). Additionally, an out-of-lock (OOL) condition is provided for debug purposes. This does not trigger a failsafe event, but does indicate potential difficulty with the APLL1. A lock status flag is provided out of APLL1, and the OOL is defined by exceeding a user-defined threshold value (register 0x00116). The lock status is a flag indicating when APLL1 is making a correction to maintain synchronization. The flag is continuously sampled. If enough active flags are sampled in a row to exceed the user-defined threshold, this condition is reported via the system status register (0x00125).
RESET INITIAL (Y IS THE ACTIVE SET) USER COMMAND GO_CLOCKS PRIMARY (X IS THE ACTIVE SET) FAILSAFE ENABLED AND FAILSAFE EVENT FAILSAFE RETURN TO NONFALLBACK STATE FS_1 FAILSAFE ENABLED AND FAILSAFE EVENT FAILSAFE RETURN TO FALLBACK STATE TO_SECONDARY (Y IS THE ACTIVE SET, ASSERT FALLBACK FLAG) FIXED SECONDARY MODE USER COMMAND CLEAR_FALLBACK FALLBACK TYPE ? ROTATING SECONDARY MODE SECONDARY (Y IS THE ACTIVE SET) FAILSAFE ENABLED AND FAILSAFE EVENT FAILSAFE RETURN TO NONFALLBACK STATE FS_2 FAILSAFE ENABLED AND FAILSAFE EVENT FAILSAFE RETURN TO FALLBACK STATE TO_PRIMARY (X IS THE ACTIVE SET, ASSERT FALLBACK FLAG) FALLBACK ENABLED AND FALLBACK EVENT ROTATING SECONDARY MODE FALLBACK ENABLED AND FALLBACK EVENT
FIXED SECONDARY MODE
FALLBACK TYPE ?
USER COMMAND CLEAR_FALLBACK
5-9421 (F)
Figure 25. T8110 Clock Failsafe States
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7 Clock Architecture (continued)
Table 66. Clock Failsafe State Descriptions Clock Failsafe State FS_1 Description APLL1 REFCLK is forced to XTAL1-div-4. FAILSAFE FLAG is asserted. Exit To PRIMARY Exit Condition User issues FAILSAFE_RETURN to nonfallback state command (set register 0x00114 bit 0).
TO_SECONDARY User issues FAILSAFE_RETURN to fallback state command (set register 0x00114 bit 1). SECONDARY User issues FAILSAFE_RETURN to non-fallback state command (set register 0x00114 bit 0). User issues FAILSAFE_RETURN to fallback state command (set register 0x00114 bit 1).
FS_2
APLL1 REFCLK is forced to XTAL1-div-4. FAILSAFE FLAG is asserted.
TO_PRIMARY
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8 Frame Group and FG I/O
There are eight independently programmable T8110 frame group/FGIO signals, FG[7:0]. In the frame group mode, the pin is an 8 kHz frame reference output, with programmable pulse width, polarity, and delay offset from the internally generated frame reference. In the FGIO mode, the pin behaves as a general-purpose register bit, with programmable direction (IN or OUT) and read masking. The FG7 signal allows for an additional mode of operation, providing a timer via a 16-bit programmable counter. Table 67. Frame Group and FG I/O Register Map DWORD Address (20 bits) 0x00400 0x00410 0x00420 0x00430 0x00440 0x00450 0x00460 0x00470 0x00474 0x00480 Register Byte 3 FG0 rate FG1 rate FG2 rate FG3 rate FG4 rate FG5 rate FG6 rate FG7 rate FG7 mode upper Reserved Byte 2 FG0 width FG1 width FG2 width FG3 width FG4 width FG5 width FG6 width FG7 width FG7 mode lower FGIO R/W Byte 1 FG0 upper start FG1 upper start FG2 upper start FG3 upper start FG4 upper start FG5 upper start FG6 upper start FG7 upper start FG7 counter high byte FGIO read mask Byte 0 FG0 lower start FG1 lower start FG2 lower start FG3 lower start FG4 lower start FG5 lower start FG6 lower start FG7 lower start FG7 counter low byte FGIO data register
8.1 Frame Group Control Registers
8.1.1 FGx Lower and Upper Start Registers The FGx lower and upper start registers provide a 12-bit delay offset value for the corresponding frame group bit. Offsets are relative to the T8110 internally generated 8 kHz frame reference and have a resolution down to one 32.768 MHz clock period (30.5 ns increments). Table 68. FGx Lower and Upper Start Registers Byte Address 0x00400 0x00410 0x00420 0x00430 0x00440 0x00450 0x00460 0x00470 0x00401 (0x00411) (0x00421) (0x00431) (0x00441) (0x00451) (0x00461) (0x00471) Name FG0 Lower Start (FG1 Lower Start) (FG2 Lower Start) (FG3 Lower Start) (FG4 Lower Start) (FG5 Lower Start) (FG6 Lower Start) (FG7 Lower Start) FG0 Upper Start (FG1 Upper Start) (FG2 Upper Start) (FG3 Upper Start) (FG4 Upper Start) (FG5 Upper Start) (FG6 Upper Start) (FG7 Upper Start) Bit(s) 7:0 Mnemonic F0LLR (F1LLR) (F2LLR) (F3LLR) (F4LLR) (F5LLR) (F6LLR) (F7LLR) F0ULR (F1ULR) (F2ULR) (F3ULR) (F4ULR) (F5ULR) (F6ULR) (F7ULR) Value Function
LLLL LLLL Lower 8 bits of 12-bit start offset.
7:0
0000 LLLL Upper 4 bits of 12-bit start offset.
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8 Frame Group and FG I/O (continued)
8.1.2 FGx Width Registers The FGx width registers control the polarity and the pulse widths generated for the corresponding frame group bit. The pulse-width programming works in conjunction with the FGx rate registers to provide 1-bit, 2-bit, 4-bit, 1-byte, and 2-byte wide pulses for any of the available frame group rates (see Table 69). Table 69. FGx Width Registers Byte Address 0x00402 (0x00412) (0x00422) (0x00432) (0x00442) (0x00452) (0x00462) (0x00472) Name FG0 Width (FG1 Width) (FG2 Width) (FG3 Width) (FG4 Width) (FG5 Width) (FG6 Width) (FG7 Width) Bit(s) Mnemonic 7 F0ISB (F1ISB) (F2ISB) (F3ISB) (F4ISB) (F5ISB) (F6ISB) (F7ISB) F0WSP (F1WSP) (F2WSP) (F3WSP) (F4WSP) (F5WSP) (F6WSP) (F7WSP) Value 0 1 Function Generate active-high pulse (default). Generate active-low pulse.
6:0
000 0000 000 0001 000 0010 000 0100 001 0000 010 0000
1-bit wide pulse (default). 1-bit wide pulse. 2-bit wide pulse. 4-bit wide pulse. 1-byte wide pulse. 2-byte wide pulse.
8.1.3 FGx Rate Registers The FGx rate registers either enable FGIO operation* or work in conjunction with FGx width registers to provide various width frame group pulses at rates of 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz. Table 70. FGx Rate Registers Byte Address 0x00403 (0x00413) (0x00423) (0x00433) (0x00443) (0x00453) (0x00463) (0x00473) Name FG0 Rate (FG1 Rate) (FG2 Rate) (FG3 Rate) (FG4 Rate) (FG5 Rate) (FG6 Rate) (FG7 Rate) Bit(s) Mnemonic 7:0 F0RSR (F1RSR) (F2RSR) (F3RSR) (F4RSR) (F5RSR) (F6RSR) (F7RSR) Value 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0000 1001 Function Off (default). FGIO enabled* (not used as a frame group). FGx rate = 2.048 MHz. FGx rate = 4.096 MHz. FGx rate = 8.192 MHz. FGx rate = 16.384 MHz.
* FGIO operation is controlled at registers 0x00480--482. Refer to Section 8.3 on page 93.
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8 Frame Group and FG I/O (continued)
8.2 FG7 Timer Option
The FG7 signal allows for an added function of a timer output, via a 16-bit programmable counter. 8.2.1 FG7 Counter (Low and High Byte) Registers The FG7 counter (low and high byte) registers set the timer value. The timer is actually a divider, so the value entered must be [divider value - 1], i.e., 0000000000000011 would yield a div-by-4 operation. The FG7 mode lower register enables the timer option, with two clock source options: T8110 internal frame or an external timer clock via the FG6 signal. The FG7 mode upper register controls the shape of the timer pulse. For more details, see Section 8.4.3 on page 97. Table 71. FG7 Counter (Low and High Byte) Registers Byte Address Name Bit 7:0 7:0 7:0 Mnemonic FCLLR FCULR F7MSR Value LLLL LLLL LLLL LLLL 0000 0000 0000 0001 0000 0010 0 1 000 001 010 100 0001 0010 0100 1000 Function Lower 8 bits of 16-bit counter value. Upper 8 bits of 16-bit counter value. Normal operation* (default). Enable timer, clock = internal frame. Enable timer, clock = external FG6. Normal FG7 timer output, high pulses (default). Inverted FG7 timer output, low pulses. FG7 timer output off (default). FG7 timer output = square wave. FG7 timer output = carry out pulse. FG7 timer output = programmable pulse. Programmable pulse width = 30.5 ns. Programmable pulse width = 61.0 ns. Programmable pulse width = 91.5 ns. Programmable pulse width = 122 ns.
0x00474 FG7 Counter, Low Byte 0x00475 FG7 Counter, High Byte 0x00476 FG7 Mode Lower
0x00477 FG7 Mode Upper
7
FCISB
6:4
F7SSP
3:0
F7WSN
* Normal operation allows frame group or FGIO control via registers 0x00470--473. Enabling the counter overrides 0x00470--473 settings. Square wave is only available when FG7 counter high/low value is a binary multiple 1, 2, 4, 8, 16, etc. Other values yield a carry out pulse shape. Carry out pulse is active for one FG7 timer clock period. Programmable pulses are based on T8110 internal 32.768 MHz clock periods.
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8 Frame Group and FG I/O (continued)
8.3 FGIO Control Registers
8.3.1 FGIO Data Register The FGIO data register provides read/write access and write storage to/from any FG signals being used as general-purpose register bits. Writes to FGIO work in conjunction with the corresponding FGIO enabled settings in the FGx rate registers. Reads are maskable, controlled via register 0x00481. Table 72. FGIO Data Register Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 8.3.2 FGIO Read Mask Register The FGIO read mask register controls the masking of any FG signals being used as general-purpose register bits on a read access to the FGIO register. Table 73. FGIO Read Mask Register Byte Address 0x00481 Name FGIO Read Mask Bit(s) Mnemonic 7 6 5 4 3 2 1 0 F7MEB F6MEB F5MEB F4MEB F3MEB F2MEB F1MEB F0MEB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Unmask FGIO bit 7 (default). Mask FGIO bit 7, return 0 on a read. Unmask FGIO bit 6 (default). Mask FGIO bit 6, return 0 on a read. Unmask FGIO bit 5 (default). Mask FGIO bit 5, return 0 on a read. Unmask FGIO bit 4 (default). Mask FGIO bit 4, return 0 on a read. Unmask FGIO bit 3 (default). Mask FGIO bit 3, return 0 on a read. Unmask FGIO bit 2 (default). Mask FGIO bit 2, return 0 on a read. Unmask FGIO bit 1 (default). Mask FGIO bit 1, return 0 on a read. Unmask FGIO bit 0 (default). Mask FGIO bit 0, return 0 on a read. F7IOB F6IOB F5IOB F4IOB F3IOB F2IOB F1IOB F0IOB Value L L L L L L L L FGIO bit 7 value. FGIO bit 6 value. FGIO bit 5 value. FGIO bit 4 value. FGIO bit 3 value. FGIO bit 2 value. FGIO bit 1 value. FGIO bit 0 value. Function
0x00480 FGIO Data Register
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8 Frame Group and FG I/O (continued)
8.3.3 FGIO R/W Register The FGIO R/W register provides direction control for any of the FG signals being used as general-purpose register bits. Table 74. FGIO R/W Register Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 F7DSB F6DSB F5DSB F4DSB F3DSB F2DSB F1DSB F0DSB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function FGIO bit 7 direction is input (default). FGIO bit 7 direction is output. FGIO bit 6 direction is input (default). FGIO bit 6 direction is output. FGIO bit 5 direction is input (default). FGIO bit 5 direction is output. FGIO bit 4 direction is input (default). FGIO bit 4 direction is output. FGIO bit 3 direction is input (default). FGIO bit 3 direction is output. FGIO bit 2 direction is input (default). FGIO bit 2 direction is output. FGIO bit 1 direction is input (default). FGIO bit 1 direction is output. FGIO bit 0 direction is input (default). FGIO bit 0 direction is output.
0x00482 FGIO R/W
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8 Frame Group and FG I/O (continued)
8.4 FG Circuit Operation
Each of the eight frame group signals FG[7:0] operate independently and have multiple uses. Refer to Figure 26 below.
n As programmable 8 kHz frame reference outputs (frame group) n As general-purpose register I/O bits (FGIO) n As a programmable timer (FG7 only) n As external interrupt input signals n As diagnostic observation points for internal test-points
MASTER ENABLE REGISTER (0x00103) TESTPOINT DIAGNOSTIC CONTROL T8110 TESTPOINTS FGIOX R/W FGX RATE FGX WIDTH FGX UPPER/ LOWER START ADDR OUTPUT ENABLE FGx ENABLE LOGIC
OFFSET DETECT
PULSE GENERATOR
T8110 INTERNAL FRAME FROM FG6 INPUT PROGRAMMABLE TIMER (FG7 ONLY)
FGX FG7 MODE FG7 COUNTER HI/LO BYTE FGIO DATA REGISTER WRITES FROM REGISTER ACCESS INTERFACE FGIO DATA REGISTER READS TO REGISTER ACCESS INTERFACE IF DIRECTION = OUTPUT, RETURN THE DATA REG CONTENTS ON A READBACK, ELSE RETURN THE I/O PIN VALUE.
FGIOX DATA REG
FGIOX READ MASK FGIOX R/W FG AS EXTERNAL INTERRUPT TO INTERRUPT CONTROLLER
5-9428a (F)
Figure 26. FG[7:0] Functional Paths
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8 Frame Group and FG I/O (continued)
8.4.1 Frame Group 8 kHz Reference Generation Any of the T8110 FG signals may be used as programmable 8 kHz frame reference outputs. There are two sets of control required, an offset delay from internal frame center, and pulse shaping. The offset delay is provided via the FGx upper/lower start address registers. The delay is relative to the T8110 internal frame center, and the 12 bits used allow for 4096 different offsets, in increments of one 32.768 MHz clock period (30.5 ns). Pulse shaping is controlled via the FGx width and FGx rate registers. Pulses may be programmed to be active-high or active-low. Pulse width can be either 1-bit, 2-bit, 4-bit, 1-byte or 2-byte wide (relative to the rate setting*), with allowable rate settings of 2.048 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz.
*Pulse widths are bit times or multiples of bit times, for each applicable rate: RATE BIT TIME 2.048 Mbits/s 488 ns 4.096 Mbits/s 244 ns 8.192 Mbits/s 122 ns 16.384 Mbits/s 61 ns
Frame Center bitclock rate (2, 4, 8, or 16MHz) T8110 internal frame timeslot 31, 63, 127 or 255 0 1 2 3 4
FG(x), 1-bit width, offset = 0 FG(x), 2-bit width, offset = 0 FG(x), 4-bit width, offset = 0
FG(x), 1-byte width, offset = 0 FG(x), 2-byte width, offset = 0
Notes: Frame group signals shown with offset = 0 (default). At offset = 0, the pulse starts at frame center. Nonzero offsets denote 32.768 MHz period increments (30.5 ns) from frame center. There are up to 4096 increments within an 8 kHz frame period. Offsets may be programmed in the range from 0--4095. Frame group signals are shown as active high pulses (default)--they may be programmed as active-low pulses. Diagram shows frame group pulse widths relative to bit-clock rate and time-slot width. This is applicable for any of the four frame group data rates (2 Mbits/s, 4 Mbits/s, 8 Mbits/s, or 16 Mbits/s).
Figure 27. Frame Group 8 kHz Reference Timing 96 Agere Systems Inc.
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8 Frame Group and FG I/O (continued)
8.4.2 FGIO General-Purpose Bits Any of the T8110 FG signals may be used as general-purpose I/O bits. Each FG bit used as FGIO is configured by enabling the FGIO function via the FGx rate register(s) and setting the direction via the appropriate bits in the FGIO R/W register. For write access to the FGIO, the FGIO data register is used to hold data for output to the FG pin(s). Read accesses are maskable via the FGIO read mask register. For read access from the FGIO, the logical state of the FG[7:0] signals is returned if unmasked. If an FGIO bit is masked, a read access returns 0. 8.4.3 Programmable Timer (FG7 Only) The FG7 signal can be used as a programmable timer output, via the FG7 mode upper/lower, and FG7 counter high and low byte registers. The FG7 timer is simply a clock divider. The FG7 counter high/low provides a 16-bit [divider value - 1]. Note: [divider value - 1], i.e., a value of 0000000000000011 yields a div-by-4 operation. The FG7 mode lower register enables the counter and selects between two clock sources into the counter: either the T8110 internal frame (8 kHz) or an external clock via the FG6 input. The FG7 mode upper register controls the output pulse shape. The output can be inverted or noninverted and shaped as either a square wave, a carryout pulse, or a programmable-width pulse.
n Square wave. This option is applicable only for divide operations that are binary multiples (i.e., div-by-2, div-by4, div-by-8, div-by-16, div-by-65536). Nonbinary divide operations while square wave is selected result in a carryout pulse.
n Carryout pulse. The output is a pulse, width = one FG7 timer clock period. n Programmable-width pulse. The timer output is synchronized to the T8110 32.768 MHz clock domain and can be
programmed for 1, 2, 3, or 4, 32.768 MHz clock periods in width (30.5 ns, 61 ns, 91.5 ns, or 122 ns). 8.4.4 FG External Interrupts All FG signals are internally connected as inputs to the interrupt controller logic. Any FG signal, whether an output or an input, may be used to trigger interrupts. When a T8110 FG signal is used as an externally sourced input into the interrupt controller logic, it must be in input mode (i.e., shut-off, FGx rate register(s) FxRSR = 0000 0000). An FG signal in output mode may also be used for interrupts (i.e., an 8 kHz periodic signal, see Section 8.4.1 on page 96). The interrupt control registers (0x00600--603) control how the FG inputs are handled (for more details, refer to Section 12.1 on page 113). 8.4.5 FG Diagnostic Test Point Observation Any of the T8110 FG signals may be used to observe a predefined set of internal test-points. Each FG bit used as a test-point output is enabled via diagnostic register 0x00140, FG test-point enable. Settings in this register override the FGx rate and FGIO R/W register, and force the selected bits to be test-point outputs, see Section 13.1 on page 128 and Table 103 on page 128.
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9 General-Purpose I/O
There are eight independent T8110 GPIO signals, GP[7:0]. These pins behave as general-purpose register bits, with programmable direction (in or out) and read masking. The GP0 and GP1 signals allow for an additional mode of operation, providing dedicated output signals to indicate A clock and B clock mastering for H.110 bus applications.
9.1 GPIO Control Registers
Table 75. GPIO Register DWORD Address (20 bits) 0x00500 Register Byte 3 GPIO override Byte 2 GPIO R/W Byte 1 GPIO read mask Byte 0 GPIO data register
9.1.1 GPIO Data Register The GPIO data register provides read/write access and write storage to/from any GP signals being used as general-purpose register bits. Reads from GPIO are maskable, controlled via register 0x00501. Table 76. GPIO Data Register Byte Address Name Bit(s) 7 6 5 4 3 2 1 0 Mnemonic G7IOB G6IOB G5IOB G4IOB G3IOB G2IOB G1IOB G0IOB Value L L L L L L L L Function GPIO bit 7 value. GPIO bit 6 value. GPIO bit 5 value. GPIO bit 4 value. GPIO bit 3 value. GPIO bit 2 value. GPIO bit 1 value. GPIO bit 0 value.
0x00500 GPIO Data Register
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9 General-Purpose I/O (continued)
9.1.2 GPIO Read Mask Register The GPIO read mask register controls the masking of any GP signals being used as general-purpose register bits on a read access to the GPIO register. Table 77. GPIO Read Mask Register
Byte Address 0x00501 Name GPIO Read Mask Bit(s) 7 6 5 4 3 2 1 0 Mnemonic G7MEB G6MEB G5MEB G4MEB G3MEB G2MEB G1MEB G0MEB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Unmask GPIO bit 7 (default). Mask GPIO bit 7, return 0 on a read. Unmask GPIO bit 6 (default). Mask GPIO bit 6, return 0 on a read. Unmask GPIO bit 5 (default). Mask GPIO bit 5, return 0 on a read. Unmask GPIO bit 4 (default). Mask GPIO bit 4, return 0 on a read. Unmask GPIO bit 3 (default). Mask GPIO bit 3, return 0 on a read. Unmask GPIO bit 2 (default). Mask GPIO bit 2, return 0 on a read. Unmask GPIO bit 1 (default). Mask GPIO bit 1, return 0 on a read. Unmask GPIO bit 0 (default). Mask GPIO bit 0, return 0 on a read.
9.1.3 GPIO R/W Register The GPIO R/W register provides direction control for any of the GP signals being used as general-purpose register bits. Table 78. GPIO R/W Register
Byte Address 0x00502 Name GPIO R/W Bit(s) 7 6 5 4 3 2 1 0 Mnemonic G7DSB G6DSB G5DSB G4DSB G3DSB G2DSB G1DSB G0DSB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Function bit 7 direction is input (default). bit 7 direction is output. bit 6 direction is input (default). bit 6 direction is output. bit 5 direction is input (default). bit 5 direction is output. bit 4 direction is input (default). bit 4 direction is output. bit 3 direction is input (default). bit 3 direction is output. bit 2 direction is input (default). bit 2 direction is output. bit 1 direction is input (default). bit 1 direction is output. bit 0 direction is input (default). bit 0 direction is output.
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9 General-Purpose I/O (continued)
9.1.4 GPIO Override Register Table 79. GPIO Override Register Byte Address Name Bit(s) Mnemonic 7:3 2 1 0 Reserved G2OEB G1OEB G0OEB Value 0000 0 0 1 0 1 0 1 Function NOP (default). GPIO bit 2 is GPIO (default). GPIO bit 2 is PCI_RST# indicator. GPIO bit 1 is GPIO (default). GPIO bit 1 B-master indicator output. GPIO bit 0 is GPIO (default). GPIO bit 0 A-master indicator output.
0x00503 GPIO Override
9.2 GP Circuit Operation
The eight general-purpose I/O group signals GP[7:0] each operate independently and have multiple uses. Please refer to Figure 28 on page 100.
n As general-purpose register I/O bits (GPIO) n As H.110 bus clock master indicators (GP0, GP1 only) n As external interrupt input signals n As diagnostic observation points for internal test-points
MASTER ENABLE REGISTER (0x00103) TESTPOINT DIAGNOSTIC CONTROL T8110 TESTPOINTS GPIOX R/W GPIO OVERRIDE GPx ENABLE LOGIC
GP0: A-CLOCK MASTER INDICATOR (0x00220 bit 4) GP1: B-CLOCK MASTER INDICATOR (0x00220 bit 5) GP2: PCI_RST# INDICATOR
OUTPUT ENABLE
GPIO DATA REGISTER WRITES FROM REGISTER ACCESS INTERFACE GPIO DATA REGISTER READS TO REGISTER ACCESS INTERFACE
GPIOX DATA REG
IF DIRECTION = OUTPUT, RETURN THE DATA REG CONTENTS ON A READBACK, ELSE RETURN THE I/O PIN VALUE.
GPX
GPIOX READ MASK GPIOX R/W GP AS EXTERNAL INTERRUPT TO INTERRUPT CONTROLLER
5-9427a (F)
Figure 28. GP[7:0] Functional Paths 100 Agere Systems Inc.
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9 General-Purpose I/O (continued)
9.2.1 GPIO General-Purpose Bits Any of the T8110 GP signals may be used as general-purpose I/O bits. Each GP bit used as GPIO is configured by setting the direction via the appropriate bits in the GPIO R/W register. For write access to the GPIO, the GPIO data register is used to hold data for output to the GP pin(s). Read accesses are maskable via the GPIO read mask register. For read access from the GPIO, the logical state of the GP[7:0] signals is returned if unmasked. If a GPIO bit is masked, a read access returns 0. 9.2.2 GP Dual-Purpose Bits GPIO (Override) 9.2.2.1 GP H.110 Clock Master Indicators (GP0, GP1 Only) An additional function is provided for GP0 and GP1 only, controlled via the GPIO override register. GP0 may be used as a dedicated output (set GPIO override register bit 0), which transmits the state of the T8110 A clock master enable (register 0x00220, bit 4). This output is intended to drive the external A clock FETs required for H.110 bus mastering. GP1 may be used as a dedicated output (set GPIO override register bit 1), which transmits the state of the T8110 B clock master enable (register 0x00220, bit 5). This output is intended to drive the external B clock FETs required for H.110 bus mastering. 9.2.2.2 PCI_RST# Indicator (GP2 Only) An additional function is provided for GP2 only, controlled via the GPIO override register. GP2 may be used as a dedicated output (set GPIO override register bit 2), which forwards the state of the PCI_RST# signal. Polarity of the transmitted signal is selectable via register 0x00780 (refer to Section 11.2 on page 110). This function provides access to a forwarded PCI_RST# signal by external devices hanging off the minibridge port. 9.2.3 GP External Interrupts Any of the T8110 GP signals may be used as externally sourced inputs into the interrupt controller logic. Each GP bit used as an interrupt input must be shut off by setting the appropriate GPIO R/W register bit to be input. The interrupt control registers (0x00604--607) control how the GP inputs are handled. For more details, see Section 12.1 on page 113. 9.2.4 GP Diagnostic Test Point Observation Any of the T8110 GP signals may be used to observe a predefined set of internal test-points. Each GP bit used as a test-point output is enabled via diagnostic register 0x00142, GP test-point enable. Settings in this register override the GPIO R/W register and force the selected bits to be test-point outputs (refer to Section 13.1 on page 128, and Table 105 on page 130).
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10 Stream Rate Control
There are a total of 64 data streams, divided into 16 stream groups of four streams each, as shown below. Table 80. T8110 Serial Stream Groupings Stream Group H-bus group A H-bus group B H-bus group C H-bus group D H-bus group E H-bus group F H-bus group G H-bus group H L-bus group A L-bus group B L-bus group C L-bus group D L-bus group E L-bus group F L-bus group G L-bus group H Stream Bits CT_D[0:3] CT_D[4:7] CT_D[8:11] CT_D[12:15] CT_D[16:19] CT_D[20:23] CT_D[24:27] CT_D[28:31] L_D[0:3] L_D[4:7] L_D[8:11] L_D[12:15] L_D[16:19] L_D[20:23] L_D[24:27] L_D[28:31]
The H-bus group operational frequencies are selectable between 2.048 MHz, 4.096 MHz, and 8.192 MHz. The L-bus groups may operate at 2.048 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz, which is implemented as multiplexed 8.192 MHz streams. (For more details, see Section 10.2.2 on page 104).
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10 Stream Rate Control (continued)
10.1 H-Bus Stream Rate Control Registers
10.1.1 H-Bus Rate Registers The H-bus rate registers control the serial data stream rate of operation for each of the H-bus stream groups, A--H. The upper nibble controls groups B, D, F, and H. The lower nibble controls groups A, C, E, and G. Table 81. H-Bus Rate Registers DWORD Address (20 bits) 0x00300 Byte Address 0x00300 (0x00301) (0x00302) (0x00303) Name H-bus Rate B/A (H-bus Rate D/C) (H-bus Rate F/E) (H-bus Rate H/G) Byte 3 H-bus rate H/G Bit(s) Mnemonic 7:4 HBRSN (HDRSN) (HFRSN) (HHRSN) HARSN (HCRSN) (HERSN) (HGRSN) Register Byte 2 Byte 1 H-bus rate F/E H-bus rate D/C Value 0000 0010 0100 1000 0000 0010 0100 1000 H-bus H-bus H-bus H-bus H-bus H-bus H-bus H-bus Function group B(D, F, H) off (default). group B(D, F, H) rate = 2.048 MHz. group B(D, F, H) rate = 4.096 MHz. group B(D, F, H) rate = 8.192 MHz. group A(C, E, G) off (default). group A(C, E, G) rate = 2.048 MHz. group A(C, E, G) rate = 4.096 MHz. group A(C, E, G) rate = 8.192 MHz. Byte 0 H-bus rate B/A
3:0
10.2 L-Bus Stream Rate Control Registers
10.2.1 L-Bus Rate Registers The L-bus rate registers control the serial data stream rate of operation for each of the H-bus stream groups, A--H. The upper nibble controls groups B, D, F, and H. The lower nibble controls groups A, C, E, and G. Local streams have a 16.384 MHz rate option (refer to Section 10.2.2 on page 104). Table 82. L-Bus Rate Registers DWORD Address (20 Bits) 0x00320 Byte Address 0x00320 (0x00321) (0x00322) (0x00323) Name L-bus Rate B/A (L-bus Rate D/C) (L-bus Rate F/E) (L-bus Rate H/G) Register Byte 3 L-bus rate H/G Byte 2 L-bus rate F/E Value 0000 0010 0100 1000 1001 0000 0010 0100 1000 1001 Byte 1 L-bus rate D/C Function L-bus group B(D, F, H) off (default). L-bus group B(D, F, H) rate = 2.048 MHz. L-bus group B(D, F, H) rate = 4.096 MHz. L-bus group B(D, F, H) rate = 8.192 MHz. L-bus group B(D, F, H) rate = 16.384 MHz. L-bus group A(C, E, G) off (default). L-bus group A(C, E, G) rate = 2.048 MHz. L-bus group A(C, E, G) rate = 4.096 MHz. L-bus group A(C, E, G) rate = 8.192 MHz. L-bus group A(C, E, G) rate = 16.384 MHz. Byte 0 L-bus rate B/A
Bit(s) Mnemonic 7:4 LBRSN (LDRSN) (LFRSN) (LHRSN) LARSN (LCRSN) (LERSN) (LGRSN)
3:0
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10 Stream Rate Control (continued)
10.2.2 L-Bus 16.384 Mbits/s Operation Local stream 16.384 Mbits/s operation is implemented as two multiplexed 8.192 Mbits/s streams. Bits are shifted at 16.384 MHz, and 16 bits are shifted per 8.192 Mbits/s time-slot (refer to Figure 29). This operation makes use of adjacent pairs of the existing single-byte hold and shift registers for local stream operation, with the local even stream assigned as the incoming stream, and the local odd stream assigned as the outgoing stream. Pairs are assigned as LD[0,1], LD[2,3], . . . LD[30,31]. When an L-bus group is set to operate at rate of 16.384 Mbits/s, the hold and shift circuitry is configured such that the serial output of the even stream shift register feeds the serial input of the odd stream shift register (refer to Figure 30).
976 ns (ONE 8 Mbits/s TIME-SLOT) TIME-SLOT n 8.192 MHz
16.384 MHz
SERIAL DATA: L_D[EVEN] (INCOMING), L_D[ODD] (OUTGOING)
15
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5
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3
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0
INCOMING BITS ARE SAMPLED AT THE 3/4 POINT OF THE BIT TIME OFFLOAD INCOMING BYTES FROM TIME-SLOT n - 1 TO HOLDING REGISTERS, LOAD OUTGOING BYTES FOR TIME-SLOT n TO SHIFT REGISTERS OFFLOAD INCOMING BYTES FROM TIME-SLOT n TO HOLDING REGISTERS, LOAD OUTGOING BYTES FOR TIME-SLOT n + 1 TO SHIFT REGISTERS
5-9411 (F)
Figure 29. Local Stream 16.384 Mbits/s Timing
INCOMING SERIAL DATA (EVEN)
8-bit BYTE FROM DATA MEMORY
EVEN STREAM OUTGOING HOLDING REGISTER INCOMING SERIAL DATA (ODD)
8
LOCAL EVEN STREAM SHIFT REGISTER
8
EVEN STREAM INCOMING HOLDING REGISTER
8-bit BYTE TO DATA MEMORY
(NO LOCAL ODD SERIAL INPUT IF 16.384 Mbits/s OPERATION)
MS bit
OUTGOING SERIAL DATA (EVEN)
(NO LOCAL EVEN SERIAL OUTPUT IF 16.384 Mbits/s OPERATION)
16.384 Mbits/s ENABLE
8-bit BYTE FROM DATA MEMORY
ODD STREAM OUTGOING HOLDING REGISTER
8
LOCAL ODD STREAM SHIFT REGISTER
8
ODD STREAM INCOMING HOLDING REGISTER
8-bit BYTE TO DATA MEMORY
MS bit
OUTGOING SERIAL DATA (ODD)
5-9426 (F)
Figure 30. Local Stream 16.384 Mbits/s Circuit 104 Agere Systems Inc.
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10 Stream Rate Control (continued)
10.2.3 16.384 Mbits/s Local I/O Superrate This 16.384 Mbits/s rate option is available only on the local I/O streams (i.e., it is not supported as a part of the H.100/H.110 specifications). When applying the superrate option to a local I/O group, the I/O for the group is redefined and divided into two pairs of input and output. An input or an output can be selected from each pair, but both can't be used simultaneously. This leads to four possible configurations for each group. Note that inputs are always on even signals and outputs are always on odd signals. Thus, if all local groups are operated at the superrate, then the application can have 16 lines, all at 16.384 Mbits/s, in contrast to the 32 I/O lines at normal rates.
LD0
LD1
LOCAL I/O PINS
GROUP A
LD2
LD3
GROUP A CONFIGURATION AT 2.048, 4.096, OR 8.192 Mbits/s
LD0
LD0
GROUP A
LOCAL I/O PINS
LD2
LOCAL I/O PINS
GROUP A
LD1
LD1
LD2
LD3
LD3
GROUP A CONFIGURATION 1 AT 16.384 Mbits/s SUPERRATE
GROUP A CONFIGURATION 2 AT 16.384 Mbits/s SUPERRATE
LD0
LD0
GROUP A
LOCAL I/O PINS
LD2
LOCAL I/O PINS
GROUP A
LD1
LD1
LD2
LD3
LD3
GROUP A CONFIGURATION 3 AT 16.384 Mbits/s SUPERRATE
GROUP A CONFIGURATION 4 AT 16.384 Mbits/s SUPERRATE
Figure 31. Superrate I/O Configuration
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10 Stream Rate Control (continued)
The configurations are selected as a consequence of the connection programming. The data is inputted or outputted as a true 16-bit at 16.384 Mbits/s signal. Programming a 16-bit connection requires two separate byte connections, one for the MS-byte and the other for the LS-byte.
8.192 Mbits/s Stream n, Timeslot m and 8.192 Mbits/s Stream n + 1, Timeslot m
7 122 ns
6
5
4
3
2
1
0
8.192 Mbits/s input data bits are sampled at 3/4 point (91 ns) of the 122 ns bit time
61 ns
16.384 Mbits/s input data bits are sampled at 3/4 point (45 ns) of the 61 ns bit time Superrate Streampair n/n + 1, Timeslot m If Input use Stream n, if Output use Stream n + 1
15
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Programming a connection for Stream n + 1, Time Slot m writes to/reads from here
Note: n = even number, m = integer.
Programming a connection for Stream n, Time Slot m writes to/reads from here
Figure 32. Relationship Between 8.192 Mbits/s and 16.384 Mbits/s Time-Slots
Thus, programming a connection to stream n + 1 is programming a connection to the MS-byte on output pin n + 1 and programming a connection to stream n is programming a connection to the LS-byte on output pin n + 1. Similarly, programming a connection from stream n + 1 is programming a connection from the MS-byte on input pin n and programming a connection from stream n is programming a connection from the LS-byte on input pin n. (An easier way to remember this is that the even/odd identifier becomes the MS-byte/LS-byte identifier.) As a consequence of this arrangement, the T8110 permits byte-packing at the superrate in analogous manner to subrate bit-packing.
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11 Minibridge
The T8110 provides for access to non-PCI devices from the PCI bus via the minibridge port. Note: If the T8110 is configured to interface to a microprocessor bus, the minibridge function is not applicable, and the minibridge port pins are used for the microprocessor interface. Refer to Section 5 on page 38. PCI access requests are converted to a simple interface to external devices hanging on the minibridge port. There are eight chip select outputs, a read strobe, a write strobe, a 16-bit address and 16-bit data bus. Additionally, a forwarded version of the PCI_RST# signal can be made available at the GP(2) output; refer to Section 6.1.1 on page 46 and Section 9.2.2.2 on page 101. PCI_AD[15:0], during the address phase, is DIRECTLY MAPPED as the MB_A[15:0] address. Customers could possibly assume this, OR may assume that byte lane enables determine the state of MB_A[1:0]. There is a direct mapping of the PCI address bits to the minibridge address bits. Users must be aware that MB_A[1:0] of a minibridge transaction is a direct pass-thru from the PCI_AD[1:0] of the address phase, and for PCI MEMORY transactions (which is the only type of transaction T8110 responds to), the value is always 00. In addition, be aware that the minibridge only operates as 16-bit-only transfers, with the data positioned only on bits [15:0] of PCI_AD during the data phase.
11.1 Wait-State Control Registers
11.1.1 Minibridge Wait-State Control Registers The minibridge wait-state control registers allow for programmable assertion times for MB_CS[7:0], MB_RD, and MB_WR control outputs. Resolution for the wait-state value increments is one 65.538 MHz clock period (15.25 ns); refer to Figure 29 on page 104. Table 83. Minibridge Wait-State Control Register Map DWORD Address (20 bits) 0x00700 0x00704 0x00710 0x00714 0x00720 0x00724 0x00730 0x00734 0x00740 0x00744 0x00750 0x00754 0x00760 0x00764 0x00770 0x00774 Register Byte 3 CS0 addr setup wait CS0 addr hold wait CS1 addr setup wait CS1 addr hold wait CS2 addr setup wait CS2 addr hold wait CS3 addr setup wait CS3 addr hold wait CS4 addr setup wait CS4 addr hold wait CS5 addr setup wait CS5 addr hold wait CS6 addr setup wait CS6 addr hold wait CS7 addr setup wait CS7 addr hold wait Byte 2 CS0 read hold wait CS0 write hold wait CS1 read hold wait CS1 write hold wait CS2 read hold wait CS2 write hold wait CS3 read hold wait CS3 write hold wait CS4 read hold wait CS4 write hold wait CS5 read hold wait CS5 write hold wait CS6 read hold wait CS6 write hold wait CS7 read hold wait CS7 write hold wait Byte 1 CS0 read width wait CS0 write width wait CS1 read width wait CS1 write width wait CS2 read width wait CS2 write width wait CS3 read width wait CS3 write width wait CS4 read width wait CS4 write width wait CS5 read width wait CS5 write width wait CS6 read width wait CS6 write width wait CS7 read width wait CS7 write width wait Byte 0 CS0 read setup wait CS0 write setup wait CS1 read setup wait CS1 write setup wait CS2 read setup wait CS2 write setup wait CS3 read setup wait CS3 write setup wait CS4 read setup wait CS4 write setup wait CS5 read setup wait CS5 write setup wait CS6 read setup wait CS6 write setup wait CS7 read setup wait CS7 write setup wait
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11 Minibridge (continued)
Table 84. Minibridge Wait-State Control Registers Byte Address 0x00700 (0x00710) (0x00720) (0x00730) (0x00740) (0x00750) (0x00760) (0x00770) 0x00701 (0x00711) (0x00721) (0x00731) (0x00741) (0x00751) (0x00761) (0x00771) 0x00702 (0x00712) (0x00722) (0x00732) (0x00742) (0x00752) (0x00762) (0x00772) 0x00703 (0x00713) (0x00723) (0x00733) (0x00743) (0x00753) (0x00763) (0x00773) 0x00704 (0x00714) (0x00724) (0x00734) (0x00744) (0x00754) (0x00764) (0x00774) Name CS0 Read Setup Wait (CS1 Read Setup Wait) (CS2 Read Setup Wait) (CS3 Read Setup Wait) (CS4 Read Setup Wait) (CS5 Read Setup Wait) (CS6 Read Setup Wait) (CS7 Read Setup Wait) CS0 Read Width Wait (CS1 Read Width Wait) (CS2 Read Width Wait) (CS3 Read Width Wait) (CS4 Read Width Wait) (CS5 Read Width Wait) (CS6 Read Width Wait) (CS7 Read Width Wait) CS0 Read Hold Wait (CS1 Read Hold Wait) (CS2 Read Hold Wait) (CS3 Read Hold Wait) (CS4 Read Hold Wait) (CS5 Read Hold Wait) (CS6 Read Hold Wait) (CS7 Read Hold Wait) CS0 Addr Setup Wait (CS1 Addr Setup Wait) (CS2 Addr Setup Wait) (CS3 Addr Setup Wait) (CS4 Addr Setup Wait) (CS5 Addr Setup Wait) (CS6 Addr Setup Wait) (CS7 Addr Setup Wait) CS0 Write Setup Wait (CS1 Write Setup Wait) (CS2 Write Setup Wait) (CS3 Write Setup Wait) (CS4 Write Setup Wait) (CS5 Write Setup Wait) (CS6 Write Setup Wait) (CS7 Write Setup Wait) Bit(s) Mnemonic 7:0 R0SLR (R1SLR) (R2SLR) (R3SLR) (R4SLR) (R5SLR) (R6SLR) (R7SLR) R0WLR (R1WLR) (R2WLR) (R3WLR) (R4WLR) (R5WLR) (R6WLR) (R7WLR) R0HLR (R1HLR) (R2HLR) (R3HLR) (R4HLR) (R5HLR) (R6HLR) (R7HLR) A0SLR (A1SLR) (A2SLR) (A3SLR) (A4SLR) (A5SLR) (A6SLR) (A7SLR) W0SLR (W1SLR) (W2SLR) (W3SLR) (W4SLR) (W5SLR) (W6SLR) (W7SLR) Value LLLL LLLL Function Read cycle wait-state value, delay to leading edge of MB_RD.
7:0
LLLL LLLL
Read cycle wait-state value, assertion time for MB_RD.
7:0
LLLL LLLL
Read cycle wait-state value, delay to deassertion of MB_CS0 (1, 2, 3, 4, 5, 6, 7).
7:0
LLLL LLLL
Any cycle wait-state value, delay from beginning of cycle to assertion of MB_CS0 (1, 2, 3, 4, 5, 6, 7).
7:0
LLLL LLLL
Write cycle wait-state value, delay to leading edge of MB_WR.
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11 Minibridge (continued)
Table 84. Minibridge Wait-State Control Registers (continued) Byte Address 0x00705 (0x00715) (0x00725) (0x00735) (0x00745) (0x00755) (0x00765) (0x00775) 0x00706 (0x00716) (0x00726) (0x00736) (0x00746) (0x00756) (0x00766) (0x00776) 0x00707 (0x00717) (0x00727) (0x00737) (0x00747) (0x00757) (0x00767) (0x00777) Name CS0 Write Width Wait (CS1 Write Width Wait) (CS2 Write Width Wait) (CS3 Write Width Wait) (CS4 Write Width Wait) (CS5 Write Width Wait) (CS6 Write Width Wait) (CS7 Write Width Wait) CS0 Write Hold Wait (CS1 Write Hold Wait) (CS2 Write Hold Wait) (CS3 Write Hold Wait) (CS4 Write Hold Wait) (CS5 Write Hold Wait) (CS6 Write Hold Wait) (CS7 Write Hold Wait) CS0 Addr Hold Wait (CS1 Addr Hold Wait) (CS2 Addr Hold Wait) (CS3 Addr Hold Wait) (CS4 Addr Hold Wait) (CS5 Addr Hold Wait) (CS6 Addr Hold Wait) (CS7 Addr Hold Wait) Bit(s) Mnemonic 7:0 W0WLR (W1WLR) (W2WLR) (W3WLR) (W4WLR) (W5WLR) (W6WLR) (W7WLR) W0HLR (W1HLR) (W2HLR) (W3HLR) (W4HLR) (W5HLR) (W6HLR) (W7HLR) A0HLR (A1HLR) (A2HLR) (A3HLR) (A4HLR) (A5HLR) (A6HLR) (A7HLR) Value LLLL LLLL Function Write cycle wait-state value, assertion time for MB_WR.
7:0
LLLL LLLL
Write cycle wait-state value, delay to deassertion of MB_CS0 (1, 2, 3, 4, 5, 6, 7).
7:0
LLLL LLLL
Any cycle wait-state value, delay from deassertion of MB_CS0 (1, 2, 3, 4, 5, 6, 7) to end of cycle.
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11 Minibridge (continued)
11.2 Strobe Control Registers
The CS strobe inversion and RD-WR strobe inversion registers allow for programmable polarity of the MB_CS[7:0], MB_RD, and MB_WR minibridge control strobes. Additionally, the polarity of the forwarded PCI_RST# signal (to the GP(2) output) is selectable. Table 85. Strobe Control Registers DWORD Address (20 bits) 0x00780 Byte Address 0x00780 Register Byte 3 Reserved Name CS Strobe Inversion Byte 2 Reserved Bit(s) Mnemonic 7 6 5 4 3 2 1 0 0x00781 R/W Strobe Inversion 7:3 2 1 0 IC7SB IC6SB IC5SB IC4SB IC3SB IC2SB IC1SB IC0SB Reserved IPRSB IMRSB IMWSB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0000 0 0 1 0 1 0 1 Byte 1 RD-WR strobe inversion Byte 0 CS strobe inversion Function CS7 strobe is active-high (default). CS7 strobe is active-low. CS6 strobe is active-high (default). CS6 strobe is active-low. CS5 strobe is active-high (default). CS5 strobe is active-low. CS4 strobe is active-high (default). CS4 strobe is active-low. CS3 strobe is active-high (default). CS3 strobe is active-low. CS2 strobe is active-high (default). CS2 strobe is active-low. CS1 strobe is active-high (default). CS1 strobe is active-low. CS0 strobe is active-high (default). CS0 strobe is active-low. NOP (default). Forward direct PCI_RST# (default). Forward inverted PCI_RST#. MB_RD strobe is active-high (default). MB_RD strobe is active-low. MB_WR strobe is active-high, (default). MB_WR strobe is active-low.
11.3 Minibridge Circuit Operation
The minibridge circuit accepts PCI memory read and memory write transactions and translates them into simple asynchronous* control strobes for external devices hanging off the minibridge port. The PCI address is passed straight through to the minibridge port, so MB_A[15:0] is always DWORD-aligned (MB_A[1:0] = 00). Transactions are always 16-bit data, with the data on the PCI side always positioned at bits PCI_AD[15:0]. Byte lane enables, PCI_CBEn[3:0], are ignored for minibridge transactions. Refer to Section 4.1.6 on page 30 for more detail on the PCI side of the transactions. Refer to Figure 33 for the access cycle descriptions of the minibridge side of the transactions.
* Asynchronous relative to the PCI clock. Strobes are generated relative to the internal chip clock in multiples of 65.536 MHz clock periods.
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11 Minibridge (continued)
T8110 INTERNAL CLOCK (65.538 MHz) taccess MB_A[15:0] ADDRESS VALID
MB_CSn tasu MB_RD trdsuwait trdsu MB_D[15:0] (READ CYCLE) RD DATA VALID twrwidth MB_WR twrsuwait twrsu MB_D[15:0] (WRITE CYCLE) WRITE DATA VALID
5-9412 (F)
trdwidth
tah
trdholdwait trdh
twrholdwait
Figure 33. Minibridge Read/Write Access Cycles
Notes:
n Strobes are created based on the T8110 internal 65.536 MHz clock. MB_CS, MB_RD, and MB_WR are shown
here as active-low, but may be programmed active-high via the CS strobe inversion and RD-WR strobe inversion registers.
n User-programmable wait-states are allowed at five points for either read or write cycles:
-- Delay from valid address to MB_CSn assertion (address wait). -- Delay from MB_CSn assertion to the leading edge of the MB_RD (or MB_WR) strobe (setup wait). -- Pulse width of the MB_RD (or MB_WR) strobe (width wait). -- Delay from MB_RD (or MB_WR) trailing edge to the deassertion of MB_CSn (hold wait). -- Delay from deassertion of MB_CSn to address invalid (address wait).
n With no wait-states, the minimum access time (read or write) for the minibridge interface is 76.3 ns
(five 65.536 MHz clock cycles). Notes:
n Timing protocol. Any user-programmable wait-states are defined in increments of 65.536 MHz clock periods
(15.25 ns): -- taccess: total access time. Minimum = 76.3 ns (five clock cycles), maximum = 19.5 s (accumulation of userprogrammed wait-states). -- tasu: address setup to MB_CSn active. Minimum = 15.25 ns (one clock cycle), maximum = 3.9 s (256 clock cycles) user-programmable via CSn address wait register. -- tah: address hold from MB_CSn inactive. Minimum = 15.25 ns (one clock cycle), maximum = 3.9 s (256 clock cycles) user-programmable via CSn address wait register. -- trdsuwait: delay from MB_CSn active to leading edge of MB_RD strobe. Minimum = 15.25 ns (one clock cycle), maximum = 3.9 s (256 clock cycles) user-programmable via CSn RD setup wait register. Agere Systems Inc. 111
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11 Minibridge (continued)
-- trdwidth: MB_RD strobe pulse width. Minimum = 15.25 ns (one clock cycle), maximum = 3.9 s (256 clock cycles) user-programmable via CSn RD width wait register. -- trdholdwait: delay from MB_RD strobe trailing edge to MB_CSn inactive. Minimum = 15.25 ns (one clock cycle), maximum = 3.9 s (256 clock cycles) user-programmable via CSn RD hold wait register. -- trdsu: read cycle data setup to trailing edge RDn. Minimum = 10 ns. -- trdh: read cycle data hold from trailing edge RDn. Minimum = 0 ns. -- twrsuwait: delay from MB_CSn active to leading edge of MB_WR strobe. Minimum = 15.25 ns (one clock cycle), maximum = 3.9 s (256 clock cycles) user-programmable via CSn WR setup wait register. -- twrwidth: MB_WR strobe pulse width. Minimum = 15.25 ns (one clock cycle), maximum = 3.9 s (256 clock cycles) user-programmable via CSn WR width wait register. -- twrholdwait: delay from MB_WR strobe trailing edge to MB_CSn inactive. Minimum = 15.25 ns (one clock cycle), maximum = 3.9 s (256 clock cycles) user-programmable via CSn WR hold wait register. -- twrsu: write cycle data setup to trailing edge of MB_WR. Minimum = 30.5 ns (two clock cycles).
11.4 Minibridge Operational Addressing
The operating space (in PCI) is from 0x70000--0x7FFFF. The address presented on the minibridge side, MB_A[15:0], is a straight pass-thru of the PCI_AD[15:0] bits during the address phase of the PCI transaction. The eight chip selects decode address bits [15:13] so that the chip selects are active in the eight spaces shown in the table below. Table 86. Minibridge Operating Space (PCI) A[15:13] 000 001 010 011 100 101 110 111 PCI Space 0x70000--71FFC 0x72000--73FFC 0x74000--75FFC 0x76000--77FFC 0x78000--79FFC 0x7A000--7BFFC 0x7C000--7DFFC 0x7E000--7FFFC MB Space 0x0000--1FFC 0x2000--3FFC 0x4000--5FFC 0x6000--7FFC 0x8000--9FFC 0xA000--BFFC 0xC000--DFFC 0xE000--FFFC Chip Select 0 1 2 3 4 5 6 7
Since the upper address lines are made available on the minibridge side in addition to the chip selects, it is possible to create variations of the selected spaces using a minimal amount of external logic. Example: A (posted) write to or (delayed) read from PCI address 0x77A10 would occur at minibridge address 0x7A10, where CS3 was active. The user could choose to use the full 16-bit address (0x7A10) or use CS3 with a 13-bit address 0x1A10 (both are simultaneously available). The timing of the CS signal relative to the read, write address, and data is set by the parameters for CS3 in PCI registers 0x00730--00737.
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12 Error Reporting and Interrupt Control
12.1 Interrupt Control Registers
Table 87. Interrupt Control Register Map DWORD Address (20 bits) 0x00600 0x00604 0x00608 0x0060C 0x00610 0x00614 0x006FC Register Byte 3 Byte 2 Byte 1 Byte 0
FGIO polarity Reserved FGIO interrupt enable FGIO interrupt pending GPIO polarity Reserved GPIO interrupt enable GPIO interrupt pending System interrupt enable System interrupt enable System interrupt System interrupt high low pending high pending low Clock interrupt enable Clock interrupt enable Clock interrupt pending Clock interrupt pending high low high low CLKERR output select SYSERR output select PCI_INTA output select Arbitration control CLKERR pulse width SYSERR pulse width Reserved Reserved In-service, byte 3 In-service, byte 2 In-service, byte 1 In-service, byte 0
12.1.1 Interrupts Via External FG[7:0] Registers 12.1.1.1 FGIO Interrupt Pending Register The FGIO interrupt pending register stores detected interrupts via the FG[7:0] signals. The user can clear specific pending bits by writing 1 to that bit (write 1 to clear). Interrupts via these signals are maskable via the FGIO interrupt enable register. Table 88. FGIO Interrupt Pending Registers Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 JF7OB JF6OB JF5OB JF4OB JF3OB JF2OB JF1OB JF0OB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function No pending interrupts via FG7 (default). Pending interrupt via FG7. No pending interrupts via FG6 (default). Pending interrupt via FG6. No pending interrupts via FG5 (default). Pending interrupt via FG5. No pending interrupts via FG4 (default). Pending interrupt via FG4. No pending interrupts via FG3 (default). Pending interrupt via FG3. No pending interrupts via FG2 (default). Pending interrupt via FG2. No pending interrupts via FG1 (default). Pending interrupt via FG1. No pending interrupts via FG0 (default). Pending interrupt via FG0.
0x00600 FGIO Interrupt Pending
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12 Error Reporting and Interrupt Control (continued)
Table 88. FGIO Interrupt Pending Registers (continued) Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 JF7EB JF6EB JF5EB JF4EB JF3EB JF2EB JF1EB JF0EB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Disable (mask) interrupts via FG7 (default). Enable (unmask) interrupts via FG7. Disable (mask) interrupts via FG6 (default). Enable (unmask) interrupts via FG6. Disable (mask) interrupts via FG5 (default). Enable (unmask) interrupts via FG5. Disable (mask) interrupts via FG4 (default). Enable (unmask) interrupts via FG4. Disable (mask) interrupts via FG3 (default). Enable (unmask) interrupts via FG3. Disable (mask) interrupts via FG2 (default). Enable (unmask) interrupts via FG2. Disable (mask) interrupts via FG1 (default). Enable (unmask) interrupts via FG1. Disable (mask) interrupts via FG0 (default). Enable (unmask) interrupts via FG0.
0x00601 FGIO Interrupt Enable
The FGIO edge/level and FGIO polarity registers control how interrupts are interpreted on the GP[7:0] signals (negative edge, positive edge, low level, or high level). Table 89. FGIO Edge/Level and Polarity Registers Byte Address Name Bit(s) Mnemonic Value 7 6 5 4 3 2 1 0 IF7SB IF6SB IF5SB IF4SB IF3SB IF2SB IF1SB IF0SB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function FG7 interrupts are negative edge or low level (default). FG7 interrupts are positive edge or high level. FG6 interrupts are negative edge or low level (default). FG6 interrupts are positive edge or high level. FG5 interrupts are negative edge or low level (default). FG5 interrupts are positive edge or high level. FG4 interrupts are negative edge or low level (default). FG4 interrupts are positive edge or high level. FG3 interrupts are negative edge or low level (default). FG3 interrupts are positive edge or high level. FG2 interrupts are negative edge or low level (default). FG2 interrupts are positive edge or high level. FG1 interrupts are negative edge or low level (default). FG1 interrupts are positive edge or high level. FG0 interrupts are negative edge or low level (default). FG0 interrupts are positive edge or high level.
0x00603 FGIO Polarity
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12 Error Reporting and Interrupt Control (continued)
12.1.2 Interrupts Via External GP[7:0] 12.1.2.1 GPIO Interrupt Pending Register The GPIO interrupt pending register stores detected interrupts via the GP[7:0] signals. The user can clear specific pending bits by writing 1 to that bit (write-1-to-clear). Interrupts via these signals are maskable via the GPIO interrupt enable register. Table 90. GPIO Interrupt Pending Register Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 0x00605 GPIO Interrupt Enable 7 6 5 4 3 2 1 0 JG7OB JG6OB JG5OB JG4OB JG3OB JG2OB JG1OB JG0OB JG7EB JG6EB JG5EB JG4EB JG3EB JG2EB JG1EB JG0EB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function No pending interrupts via GP7 (default). Pending interrupt via GP7. No pending interrupts via GP6 (default). Pending interrupt via GP6. No pending interrupts via GP5 (default). Pending interrupt via GP5. No pending interrupts via GP4 (default). Pending interrupt via GP4. No pending interrupts via GP3 (default). Pending interrupt via GP3. No pending interrupts via GP2 (default). Pending interrupt via GP2. No pending interrupts via GP1 (default). Pending interrupt via GP1. No pending interrupts via GP0 (default). Pending interrupt via GP0. Disable (mask) interrupts via GP7 (default). Enable (unmask) interrupts via GP7. Disable (mask) interrupts via GP6 (default). Enable (unmask) interrupts via GP6. Disable (mask) interrupts via GP5 (default). Enable (unmask) interrupts via GP5. Disable (mask) interrupts via GP4 (default). Enable (unmask) interrupts via GP4. Disable (mask) interrupts via GP3 (default). Enable (unmask) interrupts via GP3. Disable (mask) interrupts via GP2 (default). Enable (unmask) interrupts via GP2. Disable (mask) interrupts via GP1 (default). Enable (unmask) interrupts via GP1. Disable (mask) interrupts via GP0 (default). Enable (unmask) interrupts via GP0.
0x00604 GPIO Interrupt Pending
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12 Error Reporting and Interrupt Control (continued)
12.1.2.2 GPIO Edge/Level and GPIO Polarity Registers The GPIO edge/level and GPIO polarity registers control how interrupts are interpreted on the GP[7:0] signals (negative edge, positive edge, low level, or high level). Table 91. GPIO Edge/Level and GPIO Polarity Registers Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 IG7SB IG6SB IG5SB IG4SB IG3SB IG2SB IG1SB IF0SB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function GP7 interrupts are negative edge or low level (default). GP7 interrupts are positive edge or high level. GP6 interrupts are negative edge or low level (default). GP6 interrupts are positive edge or high level. GP5 interrupts are negative edge or low level (default). GP5 interrupts are positive edge or high level. GP4 interrupts are negative edge or low level (default). GP4 interrupts are positive edge or high level. GP3 interrupts are negative edge or low level (default). GP3 interrupts are positive edge or high level. GP2 interrupts are negative edge or low level (default). GP2 interrupts are positive edge or high level. GP1 interrupts are negative edge or low level (default). GP1 interrupts are positive edge or high level. GP0 interrupts are negative edge or low level (default). GP0 interrupts are positive edge or high level.
0x00607 GPIO Polarity
12.1.3 Interrupts Via Internal System Errors
s
Table 92. System Error Interrupt Assignments System Interrupt Bit SYS15 SYS14 SYS13 SYS12 SYS11 SYS10 SYS9 SYS8 SYS7 SYS6 SYS5 SYS4 SYS3 SYS2 SYS1 SYS0 Description Clock failsafe indicator. Clock fallback indicator. PCI target, minibridge discard timer expired. PCI target, VC memory discard timer expired. PCI target, data memory discard timer expired. PCI target, minibridge protocol error. PCI target, VC memory protocol error. PCI target, data memory protocol error. PCI master, PCI bus fatal error. PCI master, external buffer lock error. PCI master, external buffer stall error. PCI master, external buffer stall warning. PCI master, external buffer overwrite warning. PCI master, external buffer initial warning. VC memory, scratchpad overflow warning. NOTIFY_QUEUE, overflow warning.
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12 Error Reporting and Interrupt Control (continued)
12.1.4 System Interrupt Pending High/Low Registers The system interrupt pending high/low registers store detected interrupts via the internal system error signals (refer to Section 6.2.5 on page 59). The user can clear specific bits by writing 1 to that bit (write-1-to-clear). Table 93. System Interrupt Pending High/Low Registers Byte Address Name Bit(s) Mnemonic Value 7 6 5 4 3 2 1 0 0x00609 System Interrupt Pending High 7 6 5 4 3 2 1 0 JS7OB JS6OB JS5OB JS4OB JS3OB JS2OB JS1OB JS0OB JSFOB JSEOB JSDOB JSCOB JSBOB JSAOB JS9OB JS8OB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function No pending interrupts via SYS7 (default). Pending interrupt via SYS7. No pending interrupts via SYS6 (default). Pending interrupt via SYS6. No pending interrupts via SYS5 (default). Pending interrupt via SYS5. No pending interrupts via SYS4 (default). Pending interrupt via SYS4. No pending interrupts via SYS3 (default). Pending interrupt via SYS3. No pending interrupts via SYS2 (default). Pending interrupt via SYS2. No pending interrupts via SYS1 (default). Pending interrupt via SYS1. No pending interrupts via SYS0 (default). Pending interrupt via SYS0. No pending interrupts via SYS15 (default). Pending interrupt via SYS15. No pending interrupts via SYS14 (default). Pending interrupt via SYS14. No pending interrupts via SYS13 (default). Pending interrupt via SYS13. No pending interrupts via SYS12 (default). Pending interrupt via SYS12. No pending interrupts via SYS11 (default). Pending interrupt via SYS11. No pending interrupts via SYS10 (default). Pending interrupt via SYS10. No pending interrupts via SYS9 (default). Pending interrupt via SYS9. No pending interrupts via SYS8 (default). Pending interrupt via SYS8.
0x00608 System Interrupt Pending Low
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12 Error Reporting and Interrupt Control (continued)
12.1.5 System Interrupt Enable High/Low Registers The system interrupt enable high/low registers allow for masking of interrupts via the internal system error signals. Table 94. System Interrupt Enable High/Low Registers Byte Address Name Bit(s) Mnemonic Value 7 6 5 4 3 2 1 0 0x0060B System Interrupt Enable High 7 6 5 4 3 2 1 0 JS7EB JS6EB JS5EB JS4EB JS3EB JS2EB JS1EB JS0EB JSFEB JSEEB JSDEB JSCEB JSBEB JSAEB JS9EB JS8EB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Disable (mask) interrupts via SYS7 (default). Enable (unmask) interrupts via SYS7. Disable (mask) interrupts via SYS6 (default). Enable (unmask) interrupts via SYS6. Disable (mask) interrupts via SYS5 (default). Enable (unmask) interrupts via SYS5. Disable (mask) interrupts via SYS4 (default). Enable (unmask) interrupts via SYS4. Disable (mask) interrupts via SYS3 (default). Enable (unmask) interrupts via SYS3. Disable (mask) interrupts via SYS2 (default). Enable (unmask) interrupts via SYS2. Disable (mask) interrupts via SYS1 (default). Enable (unmask) interrupts via SYS1. Disable (mask) interrupts via SYS0 (default). Enable (unmask) interrupts via SYS0. Disable (mask) interrupts via SYS15 (default). Enable (unmask) interrupts via SYS15. Disable (mask) interrupts via SYS14 (default). Enable (unmask) interrupts via SYS14. Disable (mask) interrupts via SYS13 (default). Enable (unmask) interrupts via SYS13. Disable (mask) interrupts via SYS12 (default). Enable (unmask) interrupts via SYS12. Disable (mask) interrupts via SYS11 (default). Enable (unmask) interrupts via SYS11. Disable (mask) interrupts via SYS10 (default). Enable (unmask) interrupts via SYS10. Disable (mask) interrupts via SYS9 (default). Enable (unmask) interrupts via SYS9. Disable (mask) interrupts via SYS8 (default). Enable (unmask) interrupts via SYS8.
0x0060A System Interrupt Enable Low
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12 Error Reporting and Interrupt Control (continued)
12.1.6 Interrupts Via Internal Clock Errors Table 95. Clock Error Interrupt Assignments Clock Interrupt Bit CLK15 CLK14 CLK13 CLK12 CLK11 CLK10 CLK9 CLK8 CLK7 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1 CLK0 Description Failsafe indicator--APLL1 reference error. DPLL2 sync input error. DPLL1 sync input error. CT_NETREF2 error. CT_NETREF1 error. /FR_COMP error. /CT_FRAME_B error. /CT_FRAME_A error. /SCLKx2 error. SCLK error. C2 error. /C4 error. /C16- error. /C16+ error. CT_C8_B error. CT_C8_A error.
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12 Error Reporting and Interrupt Control (continued)
12.1.7 Clock Interrupt Pending High/Low Registers The clock interrupt pending high/low registers store detected interrupts via the internal clock error signals (refer to Section 6.2.1 on page 56). The user can clear specific bits by writing 1 to that bit (write 1 to clear). Table 96. Clock Interrupt Pending High/Low Registers Byte Address Name Bit(s) Mnemonic Value 7 6 5 4 3 2 1 0 0x0060D Clock Interrupt Pending High 7 6 5 4 3 2 1 0 JC7OB JC6OB JC5OB JC4OB JC3OB JC2OB JC1OB JC0OB JCFOB JCEOB JCDOB JCCOB JCBOB JCAOB JC9OB JC8OB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function No pending interrupts via CLK7 (default). Pending interrupt via CLK7. No pending interrupts via CLK6 (default). Pending interrupt via CLK6. No pending interrupts via CLK5 (default). Pending interrupt via CLK5. No pending interrupts via CLK4 (default). Pending interrupt via CLK4. No pending interrupts via CLK3 (default). Pending interrupt via CLK3. No pending interrupts via CLK2 (default). Pending interrupt via CLK2. No pending interrupts via CLK1 (default). Pending interrupt via CLK1. No pending interrupts via CLK0 (default). Pending interrupt via CLK0. No pending interrupts via CLK15 (default). Pending interrupt via CLK15. No pending interrupts via CLK14 (default). Pending interrupt via CLK14. No pending interrupts via CLK13 (default). Pending interrupt via CLK13. No pending interrupts via CLK12 (default). Pending interrupt via CLK12. No pending interrupts via CLK11 (default). Pending interrupt via CLK11. No pending interrupts via CLK10 (default). Pending interrupt via CLK10. No pending interrupts via CLK9 (default). Pending interrupt via CLK9. No pending interrupts via CLK8 (default). Pending interrupt via CLK8.
0x0060C Clock Interrupt Pending Low
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12.1.8 Clock Interrupt Enable High/Low Registers The clock interrupt enable high/low registers allow for masking of interrupts via the internal clock error signals. Table 97. Clock Interrupt Enable High/Low Registers Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 0x0060F Clock Interrupt Enable High 7 6 5 4 3 2 1 0 JC7EB JC6EB JC5EB JC4EB JC3EB JC2EB JC1EB JC0EB JCFEB JCEEB JCDEB JCCEB JCBEB JCAEB JC9EB JC8EB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Disable (mask) interrupts via CLK7 (default). Enable (unmask) interrupts via CLK7. Disable (mask) interrupts via CLK6 (default). Enable (unmask) interrupts via CLK6. Disable (mask) interrupts via CLK5 (default). Enable (unmask) interrupts via CLK5. Disable (mask) interrupts via CLK4 (default). Enable (unmask) interrupts via CLK4. Disable (mask) interrupts via CLK3 (default). Enable (unmask) interrupts via CLK3. Disable (mask) interrupts via CLK2 (default). Enable (unmask) interrupts via CLK2. Disable (mask) interrupts via CLK1 (default). Enable (unmask) interrupts via CLK1. Disable (mask) interrupts via CLK0 (default). Enable (unmask) interrupts via CLK0. Disable (mask) interrupts via CLK15 (default). Enable (unmask) interrupts via CLK15. Disable (mask) interrupts via CLK14 (default). Enable (unmask) interrupts via CLK14. Disable (mask) interrupts via CLK13 (default). Enable (unmask) interrupts via CLK13. Disable (mask) interrupts via CLK12 (default). Enable (unmask) interrupts via CLK12. Disable (mask) interrupts via CLK11 (default). Enable (unmask) interrupts via CLK11. Disable (mask) interrupts via CLK10 (default). Enable (unmask) interrupts via CLK10. Disable (mask) interrupts via CLK9 (default). Enable (unmask) interrupts via CLK9. Disable (mask) interrupts via CLK8 (default). Enable (unmask) interrupts via CLK8.
0x0060E Clock Interrupt Enable Low
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12.1.9 Interrupt Servicing Registers 12.1.9.1 Arbitration Control Register The arbitration control register allows for four modes of interrupt control operation as shown below:
n Disabled. This mode bypasses any interrupt controller operation. No FG or GP inputs are allowed as external
interrupt inputs. SYSERR assertion is a simple logical OR of the internal system error bits. CLKERR assertion is a simple logical OR of the internal clock error bits.
n Flat. This mode treats all 48 possible inputs (eight from external FG[7:0], eight from external GP[7:0], 16 from
internal system errors, 16 from internal clock errors) with equal weight, and queues them for in-service via a round-robin arbitration.
n Tier, no pre-empting. This mode assigns three priority levels. The highest level is internal clock errors CLK[15:0];
next level is internal system errors SYS[15:0]; lowest level is external errors FG[7:0] and GP[7:0]. Arbitration priority encodes between the three levels. Multiple interrupts within a level are queued round-robin.
n Tier, with pre-empting. This mode is the same as tier, with the added ability to pre-empt a current in-service interrupt according to the three priority levels. Table 98. Arbitration Control Register Byte Address 0x00610 Name Arbitration Control Bit(s) Mnemonic 7:0 JAMSR Value 0000 0000 0000 0001 0000 0010 0001 0010 Function Disable interrupt controller (default). Flat structure (round-robin arbiter). Tier structure (three levels), no pre-empting. Tier structure (three levels), pre-empting.
12.1.10 PCI_INTA Output Select Register The PCI_INTA output select register controls whether the internal signal which generates SYSERR also generates a PCI interrupt PCI_INTA#. Table 99. PCI_INTA Output Select Register Byte Address Name Bit(s) Mnemonic 7:0 JSPSR Value Function
0x00611 PCI_INTA Output Select
0000 0000 Do not route SYSERR to PCI_INTA (default). 0000 0001 Route SYSERR to PCI_INTA.
12.1.10.1 SYSERR and CLKERR Output Select Register The SYSERR output select register controls how the SYSERR signal is asserted (active-high level, active-low level, active-high pulse, or active-low pulse). The SYSERR pulse-width register controls how wide the SYSERR pulse is (when selected output format = high or low pulse). Value corresponds to the number of 32.768 MHz periods - 1. The CLKERR output select register controls how the CLKERR signal is asserted (active-high level, active-low level, active-high pulse, or active-low pulse). The CLKERR pulse-width register controls how wide the CLKERR pulse is (when selected output format = high or low pulse). Value corresponds to the number of 32.768 MHz periods - 1. 122 Agere Systems Inc.
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.
Table 100. SYSERR Output Select Registers Byte Address Name Bit(s) Mnemonic 7:0 JSOSR Value 0000 0000 0000 0001 0001 0000 0001 0001 0000 0000 0000 0001 0001 0000 0001 0001 SYSERR is SYSERR is SYSERR is SYSERR is Function active-high level* (default). active-low level*. active-high single pulse. active-low single pulse.
0x00612 SYSERR Output Select
0x00616 SYSERR Pulse Width 0x00613 CLKERR Output Select
7:0 7:0
JSWSR JCOSR
LLLL LLLL SYSERR pulse-width value. CLKERR is active-high level* (default). CLKERR is active-low level*. CLKERR is active-high single pulse. CLKERR is active-low single pulse.
0x00617 CLKERR Pulse Width
clock) pending bits are cleared.
7:0
JCWSR
LLLL LLLL CLKERR pulse-width value.
* When the arbitration control is disabled (0x00610 = 0000 0000), SYSERR or CLKERR levels remain asserted until all the internal system (or 12.1.10.2 Interrupt In-Service Registers The interrupt in-service registers provide a 16-bit interrupt vector, with unique encoding to indicate which of the 48 possible interrupts is currently in-service. Table 101. Interrupt In-Service Register Byte Address 0x006FC 0x00619 Register Name Interrupt In-service Low Interrupt In-service High Bit(s) Mnemonic 7:0 7:0 Reserved JISOR Value 0000 000 0000 0000 0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101 0001 0110 0001 0111 0010 0000 0010 0001 0010 0010 0010 0011 0010 0100 0010 0101 0010 0110 0010 0111 0100 0000 0100 0001 0100 0010 0100 0011 0100 0100 0100 0101 Function Lower byte of in-service vector; returns zero. No interrupt in-service (default). FG0 interrupt in-service. FG1 interrupt in-service. FG2 interrupt in-service. FG3 interrupt in-service. FG4 interrupt in-service. FG5 interrupt in-service. FG6 interrupt in-service. FG7 interrupt in-service. GP0 interrupt in-service. GP1 interrupt in-service. GP2 interrupt in-service. GP3 interrupt in-service. GP4 interrupt in-service. GP5 interrupt in-service. GP6 interrupt in-service. GP7 interrupt in-service. SYS0 interrupt in-service. SYS1 interrupt in-service. SYS2 interrupt in-service. SYS3 interrupt in-service. SYS4 interrupt in-service. SYS5 interrupt in-service. 123
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12 Error Reporting and Interrupt Control (continued)
Table 101. Interrupt In-Service Register (continued) Byte Address 0x00619 Register Name Interrupt In-service High Bit(s) Mnemonic 7:0 Value 0100 0110 0100 0111 0100 1000 0100 1001 0100 1010 0100 1011 0100 1100 0100 1101 0100 1110 0100 1111 1000 0000 1000 0001 1000 0010 1000 0011 1000 0100 1000 0101 1000 0110 1000 0111 1000 1000 1000 1001 1000 1010 1000 1011 1000 1100 1000 1101 1000 1110 1000 1111 LLLL LLLL 0000 000 L Function SYS6 interrupt in-service. SYS7 interrupt in-service. SYS8 interrupt in-service. SYS9 interrupt in-service. SYS10 interrupt in-service. SYS11 interrupt in-service. SYS12 interrupt in-service. SYS13 interrupt in-service. SYS14 interrupt in-service. SYS15 interrupt in-service. CLK0 interrupt in-service. CLK1 interrupt in-service. CLK2 interrupt in-service. CLK3 interrupt in-service. CLK4 interrupt in-service. CLK5 interrupt in-service. CLK6 interrupt in-service. CLK7 interrupt in-service. CLK8 interrupt in-service. CLK9 interrupt in-service. CLK10 interrupt in-service. CLK11 interrupt in-service. CLK12 interrupt in-service. CLK13 interrupt in-service. CLK14 interrupt in-service. CLK15 interrupt in-service. Low-byte, virtual channel identifier. NOP. MS bit, virtual channel identifier.
0x0061A 0x0061B
Interrupt In-service, Byte 2 Interrupt In-service, Byte 3
7:0 7:1 0
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12.2 Error Reporting and Interrupt Controller Circuit Operation
T8110 errors are reported via three output signals, CLKERR, SYSERR, and PCI_INTA#. These outputs are generated by an interrupt controller circuit; refer to Figure 34. The interrupt control circuit accepts 48 interrupt inputs in all. The way in which these interrupts are arbitrated is selectable, and the means of reporting the interrupts out to the system is also selectable.
FGIO INTERRUPT ENABLE REGISTER FGIO POLARITY, FGIO EDGE/LEVEL REGISTERS FG[7:0] EDGE/LEVEL SENSE CONVERSION
FGIO INTERRUPT PENDING REGISTER
8
GP[7:0]
GPIO POLARITY, GPIO EDGE/LEVEL REGISTERS GPIO INTERRUPT ENABLE REGISTER SYSTEM INTERRUPT ENABLE REGISTERS SYSTEM ERRORS CLOCK INTERRUPT ENABLE REGISTERS CLOCK ERRORS
EDGE/LEVEL SENSE CONVERSION
GPIO INTERRUPT PENDING REGISTER
8
16
SYSTEM INTERRUPT PENDING REGISTERS CLOCK INTERRUPT PENDING REGISTERS
16
16
INTERRUPT IN-SERVICE REGISTER CLKERR SYSERR
16
ARBITRATION CONTROL REGISTER LOGICAL OR (UNMASKED CLOCK SOURCES) CLKERR OUTPUT SELECT REGISTER PCI_INTA OUTPUT SELECT REGISTER SYSERR OUTPUT SELECT REGISTER
16
ARBITRATION
CLKERR TRIGGER
SYSERR TRIGGER
EDGE/LEVEL SENSE GENERATION
PCI_INTA#
EDGE/LEVEL SENSE GENERATION
5-9425 (F)
Figure 34. Interrupt Controller
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12.2.1 Externally Sourced Interrupts Via FG[7:0], GP[7:0] Up to 16 of the 48 interrupt inputs are sourced external to the T8110, via the FG[7:0] and GP[7:0] signals. Each input is independently controlled via the interrupt control registers (refer to Section 12.1.1 on page 113 and Section 12.1.2 on page 115). Any externally sourced interrupt may be presented as active-high level, active-low level, positive edge, or negative edge sense. Each external interrupt is maskable. Any detected interrupt which is unmasked is held in an interrupt pending register, and presented to the arbitration circuit for servicing. 12.2.2 Internally Sourced System Error Interrupts Another set of 16 of the 48 interrupt inputs are sourced internally via the system error register bits (0x00126--127; refer to Section 6.2.5 on page 59). Each of these inputs is independently controlled via the interrupt control registers (refer to Section 12.1.3 on page 116). All internal system error bit interrupts are presented as active-high level sense. Each system error bit interrupt is maskable. Any detected interrupt which is unmasked is held in an interrupt pending register and presented to the arbitration circuit for servicing. 12.2.3 Internally Sourced Clock Error Interrupts Another set of 16 of the 48 interrupt inputs are sourced internally via the latched clock error register bits (0x00122--123; refer to Section 6.2.1 on page 56). Each of these inputs is independently controlled via the interrupt control registers (refer to Section 12.1.6 on page 119). All internal clock error bit interrupts are presented as active-high level sense. Each clock error bit interrupt is maskable. Any detected interrupt that is unmasked is held in an interrupt pending register and presented to the arbitration circuit for servicing. 12.2.4 Arbitration of Pending Interrupts The arbitration of the pending interrupts can be handled in one of four selectable modes: arbitration off, flat arbitration, tier arbitration with pre-empting disabled, and tier arbitration with pre-empting enabled. Interrupts are reported to the system via the SYSERR signal (and the PCI_INTA# signal, if enabled to do so). 12.2.4.1 Arbitration Off This mode only allows the 16 internal system error register bits to generate interrupts, and no arbitration takes place. The trigger for the SYSERR output is simply a logical OR of the internal system error register bits. All bits of the internal system error register must be cleared in order to rearm the SYSERR trigger in this mode. 12.2.4.2 Flat Arbitration The flat arbitration mode performs a round-robin arbitrations on all 48 interrupt sources. When a pending interrupt wins the arbitration, the in-service register is loaded with its corresponding interrupt vector, SYSERR is triggered, and that pending bit is cleared, removing it from the next round-robin arbitration cycle. The system must respond to the current in-service interrupt (refer to Section 12.2.8 on page 127), after which the next arbitration cycle takes place. 12.2.4.3 Tier Arbitration The tier arbitration creates three prioritized groups as shown below:
n Highest priority. The 16 internal latched clock error register bits. n Next highest priority. The 16 internal system error register bits. n Lowest priority. The 16 external FG[7:0] and GP[7:0] bits.
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Arbitration assigns interrupt servicing priority to the three groups. Multiple pending interrupts within the same group are arbitrated round-robin. When a pending interrupt wins the arbitration, the in-service register is loaded with its corresponding interrupt vector, SYSERR is triggered, and that pending bit is cleared, removing it from the next arbitration cycle. 12.2.4.3.1 Pre-Empting Disabled With pre-empting disabled, once a pending interrupt wins the arbitration and the in-service register is loaded with its corresponding interrupt vector, new incoming pending interrupts of higher priority must wait for the system to respond to the current in-service interrupt (refer to Section 12.2.8 on page 127), at which time another arbitration cycle takes place. 12.2.4.3.2 Pre-Empting Enabled With pre-empting enabled, an interrupt that is in-service (i.e., its interrupt vector is loaded in the in-service register and SYSERR has been triggered) can be overridden by new incoming pending interrupts of higher priority. The current in-service interrupt is pushed onto a stack for storage; the higher-priority interrupt vector is loaded into the in-service register and SYSERR is retriggered. Once all interrupts of higher priority have been serviced by the system (refer to Section 12.2.8 on page 127), the stack is popped and the original lower-priority interrupt is reissued. 12.2.5 CLKERR Output The CLKERR output signal is used to indicate any internal clocking errors. The trigger for the CLKERR output is simply a logical OR of the internal latched clock error register bits. All bits of the internal clock error register must be cleared in order to rearm the CLKERR trigger. The CLKERR trigger induces a state machine to generate the CLKERR signal in one of four possible ways: active-high level, active-low level, active-high single pulse, or activelow single pulse. 12.2.6 SYSERR Output The T8110 SYSERR output signal is used to report interrupts. Internally, the arbitration circuit provides a SYSERR trigger, which induces a state machine to generate the SYSERR signal in one of four possible ways: active-high level, active-low level, active-high single pulse, or active-low single pulse. 12.2.7 PCI_INTA# Output The internal SYSERR trigger can be enabled to also trigger a PCI interrupt via the PCI_INTA# signal. 12.2.8 System Handling of Interrupts The T8110 interrupt controller presents an interrupt to the system by triggering the SYSERR output and providing a predefined interrupt vector value at the interrupt in-service register (ISR). The system may acknowledge the interrupt in three ways as shown below:
n System reads the T8110 ISR register. This allows the arbiter to advance, and if more pending interrupts are
active, reloads the ISR with the winner of the arbitration and retriggers SYSERR.
n System clears the T8110 ISR register (via register 0x00100, soft reset; write 0x20 clears the ISR). The arbiter
advances, and if more pending interrupts are active, reloads the ISR and retriggers SYSERR.
n System resets the interrupt controller (via register 0x00100, soft reset, write 0x10 clears the ISR and all the
pending interrupt registers). All pending interrupts are cleared, and the arbiter is reset.
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13 Test and Diagnostics
13.1 Diagnostics Control Registers
The diagnostic control registers allow for various diagnostic modes (refer to Section 13.2 on page 135). Table 102. Diagnostics Control Register Map DWORD Address (20 bits) Register Byte 3 Byte 2 Diag2, GP test-point enable Byte 1 Byte 0
0x00140 Diag3, GP test-point select
Diag1, FG test-point select Diag0, FG test-point enable Diag4, state counter modes low Diag8, interrupt controller diagnostics
0x00144 Diag7, external buffer Diag6, miscellaneous Diag5, state counter RETRY timer diagnostics low modes high 0x00148 Diag11, sync-toframe command offset high Diag10, sync-toframe command offset low Diag9, interrupt controller SYSERR delay
13.1.1 FG Testpoint Enable Register The FG test-point enable register allows individual programming of FG[7:0] bits for either standard operation (as FG or FGIO) or as test-point outputs. FG test-point select controls the MUX selection for which test-points are selected. Refer to Table 104 on page 129 for test-point assignments for each FG bit. Table 103. FG Testpoint Enable Registers Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 0x00141 Diag1, FG Testpoint Select 7:0 FT7EB FT6EB FT5EB FT4EB FT3EB FT2EB FT1EB FT0EB FTPSR Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function FG7 is standard FG or FGIO bit (default). FG7 is a test-point. FG6 is standard FG or FGIO bit (default). FG6 is a test-point. FG5 is standard FG or FGIO bit (default). FG5 is a test-point. FG4 is standard FG or FGIO bit (default). FG4 is a test-point. FG3 is standard FG or FGIO bit (default). FG3 is a test-point. FG2 is standard FG or FGIO bit (default). FG2 is a test-point. FG1 is standard FG or FGIO bit (default). FG1 is a test-point. FG0 is standard FG or FGIO bit (default). FG0 is a test-point.
0x00140 Diag0, FG Testpoint Enable
LLLL LLLL Value for MUX selection of test-points output to FG[7:0]--see Table 103 on page 128.
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Table 104. FG[7:0] Internal Testpoint Assignments FG Testpoint Select Value 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 -- 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 P_S_SELECTOR Stalled FG3 Reserved Snapping FG2
FG7
FG6
FG5
FG4
i_FRAME i_FRAME i_FRAME TAR_VALID_CMD MAS_START_DMA
STATE_COUNT[10:4] (actual time-slot) STATE_COUNT_LOOKAHEAD (lookahead time-slot) STATE_COUNT_LOOKBEHIND (lookbehind time-slot) TAR_FORCE_RETRY HOST1_COMPLETE Reserved OOL threshold flag C clock enable FG1 APLL1 lock indicator B clock enable FG0 Reserved HOST1_FATAL TRCV FIFO FLUSH MRCV FIFO FLUSH
STATE_COUNT[10:4] (actual time-slot) STATE_COUNT_LOOKAHEAD (lookahead time-slot) STATE_COUNT_LOOKBEHIND (lookbehind time-slot) TRCV FIFO PERR TRCV FIFO EMPTY TRCV FIFO LASTOUT TRCV FIFO READ Terminate master done MRCV FIFO empty Reserved MRCV FIFO READ Reserved Failsafe flag Force-to-OSC4 flag Return from FS2 flag Return from FS1 flag A clock enable Encoded ABC states: 000 or 100 = DIAGS 001 = A_ONLY 010 = A_MASTER 011 = A_ERROR 101 = B_ONLY 110 = B_MASTER 111 = B_ERROR
13.1.2 GP Testpoint Enable Register The GP test-point enable register allows individual programming of GP[7:0] bits for either standard operation (as GPIO) or as test-point outputs. GP test-point select controls the MUX selection for which test-points are selected. Refer to Table 106 on page 131 for test-point assignments for each GP bit.
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Table 105. Testpoint Enable Registers Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 0x00143 Diag3, GP Testpoint Select 7:0 GT7EB GT6EB GT5EB GT4EB GT3EB GT2EB GT1EB GT0EB GTPSR Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function GP7 is standard GPIO bit (default). GP7 is a test-point. GP6 is standard GPIO bit (default). GP6 is a test-point. GP5 is standard GPIO bit (default). GP5 is a test-point. GP4 is standard GPIO bit (default). GP4 is a test-point. GP3 is standard GPIO bit (default). GP3 is a test-point. GP2 is standard GPIO bit (default). GP2 is a test-point. GP1 is standard GPIO bit (default). GP1 is a test-point. GP0 is standard GPIO bit (default). GP0 is a test-point.
0x00142 Diag2, GP Testpoint Enable
LLLL LLLL Value for MUX selection of test-points output to GP[7:0]--see Table 105 on page 130.
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Table 106. GP[7:0] Internal Testpoint Assignments GP Testpoint Select Value 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 TAR_VALID_CMD MAS_START_DMA DPLL2 lock P_S_SELECTOR
GP7
GP6
GP5
GP4
BYTEREF_16 i_FRAME
BYTEREF_8 Reserved Reserved TAR_FORCE_RETRY HOST1_COMPLETE DPLL1 lock Fallback encoded states: 000 = PRIMARY 001 = TO_PRIMARY 010 = SECONDARY 011 = TO_SECONDARY 100 = FS1 101 = FS2 110 = [reserved] 111 = INITIAL Snapping GP2
BYTEREF_4 CP8 read Reserved HOST1_FATAL
BYTEREF_2 CP8 write TXMT FIFO flush MXMT FIFO flush Reserved
1000 0000 -- 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000
Stalled GP3
Reserved GP1
Reserved GP0
STATE_COUNT[3:0] (stream) CP4 read CP4 write Reserved TXMT FIFO full MXMT FIFO full TXMT FIFO empty MXMT FIFO empty TXMT FIFO stop MXMT FIFO lastin TXMT FIFO write MXMT FIFO write CP2 read CP2 write
Reserved Fallback flag Phase alignment frame event Go_clocks indicator APLL1 feedback, 8 MHz tap CLEAR_FALLBACK indicator APLL1 feedback, 4 MHz tap FORCE_FALLBACK indicator APLL1 feedback, 2 MHz tap
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13.1.3 State Counter Modes Registers The state counter modes registers control state counter diagnostics, including the breaking of state counter carry chains, using /FR_COMP as the internal frame reference, and allowing the state counter to roll over early via a modulo function. For more details, refer to Section 13.2 on page 135. Table 107. State Counter Modes Registers Byte Address Name Bit(s) Mnemonic 7:0 7:6 5 4 3 2:0 SCMLR Reserved SCMSB FRMSB SCLSB SCULP Value Function
0x00144 Diag4, State Counter Modes Low 0x00145 Diag5, State Counter Modes High
LLLL LLLL Lower 8 bits of state counter modulo load value. 00 NOP (default). 0 Normal carry chain operation (default). 1 Break state counter carry chains. 0 Normal internal frame operation (default). 1 Use /FR_COMP as internal frame. 0 Normal counting (default). 1 State counter modulo counting. LLL Upper 3 bits of state counter modulo load value.
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13.1.4 Miscellaneous Diagnostics Low Register The miscellaneous diagnostics low register: bit 5 enables a mode to shorten the PCI target discard timers for minibridge, VC memory, and DATA memory target accesses. Bit 4 enables microprocessor access to the minibridge register space. Bit 3 enables microprocessor access to the virtual channel memory region. Bits 2 and 1 allow direct reset of the APLL2 and APLL1 feedback dividers. Bit 0 controls the TST input of the power-on reset cell. Table 108. Miscellaneous Diagnostics Low Register Byte Address Name Bit(s) 7:6 5 4 Mnemonic Reserved PDTSB MBIEB Value 00 0 1 0 1 3 VCMEB 0 1 0 1 0 1 -- Function NOP (default). PCI target discard timers normal (default). PCI target discard timers shortened. Microprocessor access to minibridge registers disabled (default). Microprocessor access to minibridge registers enabled. Microprocessor access to VC memory disabled (default). Microprocessor access to VC memory enabled. APLL2 feedback divider reset inactive (default). APLL2 feedback divider reset active. APLL1 feedback divider reset inactive (default). APLL1 feedback divider reset active. --
0x00146 Diag6, Miscellaneous Diagnostics Low
2 1 0
FB2SB FB1SB Reserved
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13 Test and Diagnostics (continued)
13.1.5 External Buffer Retry Timer Register The external buffer retry timer register provides a time-out value for external buffer accesses. Value indicates [number of 65.536 MHz periods - 1]. The retry in this context refers to receiving a BUFFER LOCKED status on the first descriptor table fetch attempt, and then retrying the fetch after the retry timer expires. Refer to Section 14.2.3.4 for more detail. Table 109. External Buffer Retry Timer Register Byte Address Name Bit(s) Mnemonic 7:0 7:6 5:4 3:2 1:0 7:0 7:0 EBOLR ICDSP ICKLP ISYLP IEXLP IASLR CFLLR Value Function
0x00147 Diag7, External Buffer Retry Timer 0x00148 Diag8, Interrupt Controller Diagnostic
0x00149 Diag9, Interrupt Controller Deassertion Delay 0x0014A Diag10, Sync-to-frame Command Delay (Lower) 0x0014B Diag11, Sync-to-frame Command Delay (Upper)
7:4 3:0
CFSEN CFHLN
LLLL LLLL RETRY timer value for external buffer access. 00 Interrupt controller, normal mode (default). 01 Interrupt controller, DIAG mode. LL DIAG mode, force CLK[1:0] errors. LL DIAG mode, force SYS[1:0] errors. LL DIAG mode, force EXT[8, 0] errors. LLLL LLLL Programmable delay to control the deassertion time of SYSERR. LLLL LLLL Low byte of 12-bit offset value for sync-toframe clock commands (GO_CLOCKS, CLEAR_FALLBACK, FORCE_FALLBACK). 0000 Disable delay mode (default). 0001 Enable delay mode. LLLL Upper 4 bits of 12-bit offset value for sync-to-frame clock commands (GO_CLOCKS, CLEAR_FALLBACK, FORCE_FALLBACK).
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13 Test and Diagnostics (continued)
13.2 Diagnostic Circuit Operation
The T8110 internal diagnostic modes are intended primarily for chip manufacturing test. The diagnostic functions include the following:
n DIAG0--3, observability of internal test-points via FG(7:0), GP(7:0):
-- Internal test-points are brought to chip I/O at FG and GP signals. Refer to Table 104 on page 129 and Table 106 on page 131 for test-point assignment.
n DIAG4--5, internal state counter diagnostic modes:
-- Break counter carry chains--this is used in conjunction with monitoring of the state counter bits at FG and GP, and breaks the 11-bit state counter into three separate pieces (bits [10:8], [7:4] and [3:0]). -- Shorten frame operation--the internally generated 8 kHz frame is bypassed in favor of the /FR_COMP input. The /FR_COMP input still denotes the frame center and may be presented at a higher frequency than 8 kHz. This is used in conjunction with the state counter modulo function, which when properly programmed allows the internal state counter to roll over coincident with the /FR_COMP frame center.
n DIAG6, microprocessor access to the virtual channel memory and minibridge register regions:
-- The VC memory region is only functionally applicable for packet payload switching, which is only available when the T8110 interface to a local PCI bus is selected. When interface to microprocessor bus is selected, this diagnostic setting allows direct access to the virtual channel memory. -- The minibridge registers are only functionally applicable for minibridge port operation and are only available when the T8110 interface to a local PCI bus is selected. When interface to microprocessor bus is selected, this diagnostic setting allows direct access to the minibridge registers.
n DIAG6, forced RESET of analog APLL1 feedback dividers:
-- The APLL1 feedback dividers are typically not reset. This diagnostic mode allows each feedback divider to be held in a reset state.
n DIAG7, external buffer RETRY timer:
-- The external buffer access protocol allows for one RETRY of a descriptor table fetch in the case of a locked external buffer. This diagnostic register allows for manipulation of the amount of time to wait before retrying a descriptor table fetch. Please see Section 14.2.3.4 on page 160 for more details.
n DIAG8, interrupt controller diagnostics:
-- When the diagnostic mode is enabled (DIAG8 register, bits 7:6 = 01), then bits 5:4 override the CLK error[1:0] inputs, bits [3:2] override the SYS error[1:0] inputs, bit 1 overrides the GP[0] input, and bit 0 overrides the FG[0] input to the interrupt controller. This allows for direct manipulation to set/clear a portion of interrupt bits from each tier group. Please see Section 12.2 on page 125 for more details.
n DIAG9, interrupt controller deassertion delay:
-- Allows a programmable deassertion time for the SYSERR signal in between back-to-back interrupts.
n DIAG10--11, sync-to-frame command delay:
-- Allows a programmable delay time from the FRAME boundary for execution of the sync-to-frame clock commands, GO_CLOCKS, CLEAR_FALLBACK, FORCE_FALLBACK.
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Data Sheet May 2001
14 Connection Control--Standard and Virtual Channel
14.1 Programming Interface
Programming the T8110 for standard and virtual channel switching requires specific access cycles to the connection memory and virtual channel memory regions. Access to any other region (data memory, minibridge, or registers) is made through a standard direct access via the interface (described starting in Section 4 on page 22). 14.1.1 PCI Interface When the T8110 PCI interface is the selected bus interface, both standard telephony and virtual channel switching are allowed. A standard telephony connection is made by writing to a location in the connection memory. A virtual channel connection requires a write to the connection memory plus a corresponding write to the virtual channel memory. 14.1.1.1 PCI Connection Memory Programming The connection memory is divided into four 2K regions, each of which handles up to 128 time slots worth of connectivity for each of 16 serial data streams. The regions include H1x0 EVEN streams (CT_D[30, 28, . . . 0]), H1x0 ODD streams (CT_D[31, 29, . . . 1]), local low streams (L_D[15:0]), and local high streams (L_D[31:16]). The connection memory locations are addressed relative to time-slot and stream. BURST access is allowed to the connection memory. In order to SKIP making/breaking a connection to a particular time slot and stream combination that gets addressed during a burst, the user must disable all the byte enables for that particular data phase. Connection memory commands are as follows:
n RESET PAGE-- resets any (up to all four) connection memory region. Address bit 15 determines whether or not
it's a reset page command. The reset page command relies on a valid internal chip clock and loops through all addresses within the connection memory region, resetting the VALID bit field. The reset page command must be presented as a PCI memory WRITE command; refer to Figure 35.
n MAKE/BREAK/QUERY-- telephony connection; refer to Figure 36. n MAKE/BREAK/QUERY-- virtual channel nonbonded connection; refer to Figure 37. n MAKE/BREAK/QUERY-- virtual channel bonded connection; refer to Figure 38.
MAKE and BREAK commands above must be presented as PCI memory write commands. QUERY commands are presented as PCI memory read commands.
ADDRESS PHASE, RESET PAGE COMMAND
31:20 BASE ADDRESS
19:16 0100
15 1
14:8 0000000
7:0 00000000
DATA PHASE, RESET PAGE COMMAND
31:25 0000000
24
23:17 0000000
16
15:9 0000000 RLH
8
7:1 0000000
0
0 = NO ACTION 1 = RESET H1x0 ODD REGION
RHO
0 = NO ACTION 1 = RESET H1x0 EVEN REGION
RHE
0 = NO ACTION 1 = RESET LOCAL HIGH REGION
0 = NO ACTION 1 = RESET LOCAL LOW REGION
RLL
5-9622 (F)
Figure 35. PCI Programming--Reset Page Command
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14 Connection Control--Standard and Virtual Channel (continued)
ADDRESS PHASE, MAKE OR BREAK TELEPHONY CONNECTION 31:20 BASE ADDRESS 19:16 0100 15 0 14:8 TIMESLOT 7 6:2 STREAM HLS 1:0 00
H-BUS/LOCAL SELECT: 0 = LOCAL STREAMS 1 = H.1x0 STREAMS DATA PHASE, MAKE OR BREAK TELEPHONY CONNECTION 31 0 30:28 000 27 26 25 24 23:20 0000 19:16 TAG 15:8 TAG 7 0
6:0 SUBRATE
PME VFC RWS MBS
0 = PATTERN MODE DISABLED 1 = PATTERN MODE ENABLED
0 = USE CURRENT FRAME 1 = USE NEXT FRAME
0 = WRITE TO DATA MEMORY 1 = READ FROM DATA MEORY
0 = MAKE CONNECTION 1 = BREAK CONNECTION
RESERVED VTC VC/TEL CONTROL 5-9623 (F)
Note: For QUERY (read cycle), a 0 in bit 27 of the data phase indicates an invalid or broken connection. A 1 in bit 27 indicates a valid connection.
Figure 36. PCI Programming--Make/Break/Query Telephony Connection
ADDRESS PHASE, MAKE OR BREAK VIRTUAL CHANNEL CONNECTION
31:20 BASE ADDRESS
19:16 0100
15 0
14:8 TIMESLOT
7 HLS
6:2 STREAM
1:0 00
H-BUS/LOCAL SELECT: 0 = LOCAL STREAMS 1 = H.1x0 STREAMS DATA PHASE, MAKE OR BREAK VIRTUAL CHANNEL CONNECTION, NO BONDING 31 1 30:28 000 27 26 25 24 00 BCC BVF RWS MBS 23:16 VC IDENTIFIER BONDED CHANNEL CONTROL 15 14:8 0000000 7 SVF VCP 0 = VC EVEN PAGE 1 = VC ODD PAGE 6:0 SUBRATE SUBRATE, VIRTUAL FRAME MARKER 0 = NO MARKER 1 = ACTIVE MARKER
BONDED CHANNEL, VIRTUAL FRAME MARKER
0 = WRITE TO DATA MEMORY 1 = READ FROM DATA MEMORY
0 = MAKE CONNECTION 1 = BREAK CONNECTION
RESERVED VTC VC/TEL CONTROL 5-9624 (F)
Note: For QUERY (read cycle), a 0 in bit 27 of the data phase indicates an invalid or broken connection. A 1 in bit 27 indicates a valid connection.
Figure 37. PCI Programming--Make/Break/Query Virtual Channel Nonbonded Connection
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14 Connection Control--Standard and Virtual Channel (continued)
ADRESS PHASE MAKE OR BREAK VIRTUAL CHANNEL CONNECTION
31:20 Base Address
19:16 0100
15 0
14:8 Time Slot
7
6:2 Stream
1:0 00
HLS
H-Bus/Local Select: 0 = Local Streams 1 = H1x0 Streams
DATA PHASE, MAKE OR BREAK VIRTUAL CHANNEL CONNECTION, BONDED
31 1
30:28 000
27 26 25 24 1
23:16 VC Identifier
15 14:13 00
12:8 Bonded Channel Depth
7:5 000
4:0 Bonded Channel Offset
BCC Bonded Channel VCP 0 = VC Even Page Control BVF Bonded Channel, Virtual 1 = VC Odd Page Frame Marker: 0 = no marker, 1 = active marker RWS 0 = W rite to Data Memory 1 = Read from Data Memory MBS 0 = Make Connection 1 = Break Connection Reserved VTC VC/Tel Control
Note: For QUERY (read cycle), a 0 in bit 27 of the data phase indicates an invalid or broken connection. A 1 in bit 27 indicates a valid connection.
Figure 38. PCI Programming--Make/Break/Query Virtual Channel Bonded Connection
14.1.1.2 PCI Virtual Channel Memory Programming The virtual channel memory is divided into two regions, the static portion and the scratchpad portion. The static portion contains two read/write fields, defining a particular virtual channel's base address and depth. The scratchpad portion contains one read/write field (depth) and one read-only field (current offset). On any write to the virtual channel memory, the scratchpad current offset is reset to zero. Virtual channel memory commands are as follows:
n A WRITE is presented as a PCI memory write command Figure 39 below. n A READ STATIC is presented as a PCI memory read command (see Figure 40 on page 139). n A READ SCRATCHPAD is presented as a PCI memory read command (see Figure 41 on page 139).
ADDRESS PHASE, VIRTUAL CHANNEL MEMORY WRITE COMMAND 31:20 BASE ADDRESS 19:16 0001 15:8 VC IDENTIFIER ADDRESS VC PAGE ADDRESS VCPA 0 = VC EVEN PAGE 1 = VC ODD PAGE DATA PHASE, VIRTUAL CHANNEL MEMORY WRITE COMMAND 31:24 SCRATCHPAD CURRENT DEPTH (SPCD) 23:18 STATIC DEPTH (STD) 17:16 00 15:12 0000 11:2 STATIC BASE ADDRESS (SBA) 1:0 00 7 6:0 0000000
VALUE OF 0 TO 63 IMPLIES 1 TO 64 DWORDS DEEP WRITING TO THIS FIELD SETS THE STARTING POSITION
VIRTUAL CHANNEL LIES ON DWORD BOUNDARIES WITHIN DATA MEMORY 5-9628 (F)
Figure 39. PCI Programming--Write Virtual Channel Command
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14 Connection Control--Standard and Virtual Channel (continued)
ADDRESS PHASE, VIRTUAL CHANNEL MEMORY READ STATIC COMMAND 31:20 BASE ADDRESS 19:16 0001 15:8 7 VC IDENTIFIER ADDRESS VC PAGE ADDRESS VCPA 0 = VC EVEN PAGE 1 = VC ODD PAGE STATIC/SCRATCHPAD SELECT 0 = STATIC ENTRIES 1 = SCRATCHPAD DATA PHASE, VIRTUAL CHANNEL MEMORY READ STATIC COMMAND SSS 6:4 000 3 0 2:0 000
31:24 00000000
23:18 STATIC DEPTH (STD)
17:16 11
15:12 0000
11:2 STATIC BASE ADDRESS (SBA)
1:0 00
RETURNS THE RELATIVE OFFSET OF DEEPEST BYTE (MAX = 255) 5-9627 (F)
Figure 40. PCI Programming--Read Virtual Channel Static Command
ADDRESS PHASE, VIRTUAL CHANNEL MEMORY READ SCRATCHPAD COMMAND
31:20 BASE ADDRESS
19:16 0001
15:8 7 VC IDENTIFIER ADDRESS VC PAGE ADDRESS VCPA 0 = VC EVEN PAGE 1 = VC ODD PAGE
6:4 000
3 1
2:0 000
STATIC/SCRATCHPAD SELECT 0 = STATIC ENTRIES 1 = SCRATCHPAD DATA PHASE, VIRTUAL CHANNEL MEMORY READ SCRATCHPAD COMMAND 31:24 SCRATCHPAD CURRENT DEPTH (SPCD) 23:16 00000000 15:8 SCRATCHPAD CURRENT OFFSET (SPCO)
SSS
7:0 00000000
VALUE OF THE COUNTER WHICH TRACKS THE NUMBER OF BYTES USED IN THE BUFFER.
MEMORY POINTER, CURRENT OFFSET WITHIN CHANNEL BUFFER. 5-9630 (F)
Figure 41. PCI Programming--Read Virtual Channel Scratchpad Command
14.1.2 Microprocessor Interface When the T8110 microprocessor interface is the selected bus interface, only standard telephony switching is allowed (no virtual channel switching). A standard telephony connection is made by writing to a location in the connection memory. There is a mode in which the virtual channel memory may be accessed via the microprocessor interface, included for diagnostic purposes only. 14.1.2.1 Microprocessor Connection Memory Programming Because the microprocessor interface only allows word or byte accesses, multiple write accesses must occur. The microprocessor connection memory access mimics the 32-bit PCI access by using a combination of the lower two address bits [1:0] and holding registers. For byte access, there are a total of three byte-wide holding registers. For word access, there is one word-wide holding register. The user must load the holding registers with the proper information first, and then write to the upper byte (or upper word) to actually move data into the connection memory; refer to Table 110.
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Data Sheet May 2001
14 Connection Control--Standard and Virtual Channel (continued)
The connection memory is divided into four 2K regions, each of which handles up to 128 time slots worth of connectivity for each of 16 serial data streams. The regions include H1x0 even streams (CT_D[30, 28, . . . 0]), H1x0 odd streams (CT_D[31, 29, . . . 1]), local low streams (L_D[15:0]), and local high streams (L_D[31:16]). The connection memory locations are addressed relative to time slot and stream. Connection memory commands are as follows:
n RESET PAGE resets any (up to all four) connection memory region (see Figure 42 on page 141). Address bit 15
determines whether or not it's a reset page command. The reset page command relies on a valid internal chip clock and loops through all addresses within the connection memory region, resetting the VALID bit field. The RESET PAGE command is presented as either two microprocessor WORD writes, or four microprocessor BYTE writes, see Table 110.
n MAKE/BREAK/QUERY, telephony connection (see Figure 43 on page 141). n MAKE/BREAK/QUERY, virtual channel nonbonded connection* (see Figure 44 on page 142). n MAKE/BREAK/QUERY, virtual channel bonded connection* (see Figure 45 on page 143).
The MAKE and BREAK commands are presented as multiple microprocessor write cycles. The QUERY command is presented as multiple microprocessor read cycles; refer to Table 110.
* Making virtual channel connections in the connection memory is for diagnostic purpose only when the microprocessor interface is selected.
Table 110. Microprocessor Programming, Connection Memory Access Word/Byte (MB_CS5) Byte Byte Byte Byte Word Word A[1:0] 00 01 10 11 0X 1X D[15:8] X X X X Data byte 1 Data byte 3 D[7:0] Access Description
Data byte 0 Write data byte 0 to a holding register, or read data byte 0 information. Data byte 1 Write data byte 1 to a holding register, or read data byte 1 information. Data byte 2 Write data byte 2 to a holding register, or read data byte 2 information. Data byte 3 Write data byte 3 plus the holding register data to connection memory, or read data byte 3 information. Data byte 0 Write data bytes 1 and 0 to a holding register, or read data bytes 1 and 0 information. Data byte 2 Write data bytes 3 and 2 plus the holding register data to connection memory, or read data bytes 3 and 2 information.
Note: Data byte n required information is shown in Figure 43--Figure 45.
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14 Connection Control--Standard and Virtual Channel (continued)
19:16 0100 15 1 14:0 000000000000000
A[19:0]
DATA BYTE 1
7:1 0000000
bit 0
DATA BYTE 0
7:1 0000000
bit 0
0 = NO ACTION 1 = RESET LOCAL HI REGION
RLH
0 = NO ACTION 1 = RESET LOCAL LO REGION
RLL
DATA BYTE 3
7:1 0000000
bit 0
DATA BYTE 2
7:1 0000000
bit 0
0 = NO ACTION 1 = RESET H-BUS ODD REGION
RHO
0 = NO ACTION 1 = RESET H-BUS EVEN REGION
RHE
Figure 42. Microprocessor Programming--Reset Page Command
A[19:0]
19:16 0100
15 0
14:8 TIME-SLOT
7
6:2 STREAM
1:0
H-BUS/LOCAL SELECT: 0 = LOCAL STREAMS 1 = H.1x0 STREAMS
HLS WORD/BYTE ADDRESS LSBITS
DATA BYTE 1
7:0 TAG (LOWER BITS)
DATA BYTE 0
7 0
6:0 SUBRATE
DATA BYTE 3
7 0
6:4 000
3
2
1
0
DATA BYTE 2
7:4 0000
3:0 TAG (UPPER BITS)
PME VFC
0 = PATTERN MODE DISABLED 1 = PATTERN MODE ENABLED
0 = USE CURRENT FRAME 1 = USE NEXT FRAME
RWS
0 = WRITE TO DATA MEMORY 1 = READ FROM DATA MEMORY
MBS VTC VC/TEL CONTROL
0 = MAKE CONNECTION 1 = BREAK CONNECTION
5-9632 (F)
Figure 43. Microprocessor Programming--Make/Break/Query Telephony Connections
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Data Sheet May 2001
14 Connection Control--Standard and Virtual Channel (continued)
A[19:0]
19:16 0100
15 0
14:8 TIMESLOT
7
6:2 STREAM
1:0
H-BUS/LOCAL SELECT: 0 = LOCAL STREAMS 1 = H.1x0 STREAMS
HLS
WORD/BYTE ADDRESS LS BITS
DATA BYTE 1
7
6:0 0000000
DATA BYTE 0
7
6:0 SUBRATE
VCP
0 = VC EVEN PAGE 1 = VC ODD PAGE
SVF
SUBRATE VIRTUAL FRAME MARKER: 0 = NO MARKER 1 = ACTIVE MARKER
DATA BYTE 3
7 1
6:4 000
3
2
1 0
0 0
DATA BYTE 2
7:0 VC IDENTIFIER
BCC BONDED CHANNEL CONTROL
BVF
BONDED CHANNEL, VIRTUAL FRAME MARKER:
RWS
0 = WRITE TO DATA MEM 1 = READ FROM DATA MEM
MBS
0 = MAKE CONNECTION 1 = BREAK CONNECTION
VTC VC/Tel Control
1447
Figure 44. Microprocessor Programming--Make/Break/Query Virtual Channel Nonbonded Connections
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14 Connection Control--Standard and Virtual Channel (continued)
A[19:0]
19:16 0100
15 0
14:8 TIMESLOT
7
6:2 STREAM
1:0
H-BUS/LOCAL SELECT: 0 = LOCAL STREAMS 1 = H.1X0 STREAMS
HLS
WORD/BYTE ADDRESS LS BITS
DATA BYTE 1
7
6:5 00
4:0 BONDED CHANNEL DEPTH
DATA BYTE 0
7:5 000
4:0 BONDED CHANNEL OFFSET
VCP
0 = VC EVEN PAGE 1 = VC ODD PAGE
DATA BYTE 3
7 1
6:4 000
3
2
1
0 1
DATA BYTE 2
7:0 VC IDENTIFIER
BCC BONDED CHANNEL CONTROL
BVF
BONDED CHANNEL, VIRTUAL FRAME MARKER: 0 = NO MARKER 1 = ACTIVE MARKER 0 = WRITE TO DATA MEM 1 = READ FROM DATA MEM
RWS
MB S
0 = MAKE CONNECTION 1 = BREAK CONNECTION
VTC VC/Tel CONTROL
1446
Figure 45. Microprocessor Programming--Make/Break/Query Virtual Channel Bonded Connection
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Data Sheet May 2001
14 Connection Control--Standard and Virtual Channel (continued)
14.1.2.2 Microprocessor Virtual Channel Memory Programming Because the microprocessor interface only allows word or byte accesses, multiple write accesses must occur. The microprocessor virtual channel memory access mimics the 32-bit PCI access by using a combination of the lower two address bits [1:0] and holding registers. For byte access, there are a total of three byte-wide holding registers. For word access, there is one word-wide holding register. The user must load the holding registers with the proper information first, and then write to the upper byte (or upper word) to actually move data into the virtual channel memory; refer to Table 111. The virtual channel memory is divided into two regions: the static portion and the scratchpad portion. The static portion contains two read/write fields, defining a particular virtual channel's base address and depth. The scratchpad portion contains one read/write field (depth) and one read-only field (current offset). On any write to the virtual channel memory, the scratchpad current offset is reset to zero. Virtual channel memory commands are as follows:
n The WRITE command is presented as a microprocessor write cycle (see Figure 46 on page 145). n The READ STATIC command is presented as a microprocessor read cycle (see Figure 47 on page 145). n The READ SCRATCHPAD command is presented as a microprocessor read cycle (see Figure 48 on page 146).
Note: Accessing the virtual channel memory is for diagnostic purpose only when the microprocessor interface is selected. Table 111. Virtual Channel Memory Access Word/Byte (MB_CS5) Byte Byte Byte Byte A[1:0] 00 01 10 11 D[15:8] X D[7:0] Access Description
Word Word
0X 1X
Data byte 0 Write data byte 0 to a holding register, or read data byte 0 information. X Data byte 1 Write data byte 1 to a holding register, or read data byte 1 information. X Data byte 2 Write data byte 2 to a holding register, or read data byte 2 information. X Data byte 3 Write data byte 3 plus the holding register data to a virtual channel memory, or read data byte 3 information. Data byte 1 Data byte 0 Write data bytes 1 and 0 to a holding register, or read data bytes 1 and 0 information. Data byte 3 Data byte 2 Write data bytes 3 and 2 plus the holding register data to a virtual channel memory, or read data bytes 3 and 2 information.
Note: Data byte n required information is shown in Figure 46--Figure 48.
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14 Connection Control--Standard and Virtual Channel (continued)
19:16 0001 15:8 VC IDENTIFIER ADDRESS 6:0 0000000
A[19:0]
7
VC PAGE ADDRESS 0 = VC EVEN PAGE 1 = VC ODD PAGE
VCPA
DATA BYTE 1
7:4 0000
3:0 STATIC BASE ADDRESS UPPER
DATA BYTE 0
7:2 STATIC BASE ADDRESS (SBA) LOWER
1:0 00
VIRTUAL CHANNEL LIES ON DWORD BOUNDARIES WITHIN DATA MEMORY
DATA BYTE 3
7:0 SCRATCHPAD CURRENT DEPTH (SPCD)
DATA BYTE 2
7:2 STATIC DEPTH (STD)
1:0 00
WRITING TO THIS FIELD SETS THE STARTING POSITION
VALUE OF 0 TO 63 IMPLIES 1 TO 64 DWORDS DEEP 5-9635 (F)
Figure 46. Microprocessor Programming--Write Virtual Channel Memory Command
A[19:0]
19:16 0001
15:8 VC IDENTIFIER ADDRESS
7
6:4 000
3 0
2:0 000
VC PAGE ADDRESS 0 = VC EVEN PAGE 1 = VC ODD PAGE
VCPA
STATIC/SCRATCHPAD SELECT 0 = STATIC ENTRIES 1 = SCRATCHPAD
SSS
DATA BYTE 1
7:4 0000
3:0 STATIC BASE ADDRESS UPPER
DATA BYTE 0
7:2 STATIC BASE ADDRESS (SBA) LOWER
1:0 00
DATA BYTE 3
7:0 00000000
DATA BYTE 2
7:2 STATIC DEPTH (STD)
1:0 11
RETURNS THE RELATIVE OFFSET OF DEEPEST BYTE (MAX = 255) 5-9636 (F)
Figure 47. Microprocessor Programming--Read Virtual Channel Static Command
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14 Connection Control--Standard and Virtual Channel (continued)
19:16 0001 15:8 VC IDENTIFIER ADDRESS 6:4 000 3 1 2:0 000
A[19:0]
7
VC PAGE ADDRESS 0 = VC EVEN PAGE 1 = VC ODD PAGE
VCPA
STATIC/SCRATCHPAD SELECT 0 = STATIC ENTRIES 1 = SCRATCHPAD
SSS
DATA BYTE 1
7:0 SCRATCHPAD CURRENT OFFSET (SPCO)
DATA BYTE 0
7:0 00000000
MEMORY POINTER, CURRENT OFFSET WITHIN CHANNEL BUFFER
DATA BYTE 3
7:0 SCRATCHPAD CURRENT DEPTH (SPCD)
DATA BYTE 2
7:0 00000000
VALUE OF THE COUNTER WHICH TRACKS THE NUMBER OF BYTES USED IN THE BUFFER 5-9637 (F)
Figure 48. Microprocessor Programming--Read Virtual Channel Scratchpad Command
14.2 Switching Operation
T8110 provides two main switching operations, standard (telephony) switching and virtual channel (packet payload) switching. The basic building block of switching is one-half simplex connections loaded into the connection memory. Each connection memory location controls data flow, either from a serial stream input to a location in data memory, or from data memory to a serial stream output. A typical telephony simplex switch connection would use one from and one to connection, each using the same data memory location. A virtual channel switch connection would only use one half simplex connection (to or from), plus control provided in virtual channel memory to initiate transfers between the data memory and an external buffer in the PCI space. 14.2.1 Memory Architecture and Configuration 14.2.1.1 Connection Memory The T8110 connection memory consists of 8192 locations, one location for each of the possible stream/time-slot combinations, to provide a full nonblocking switch for up to 128 time slots on 32 H1x0 streams (CT_D[31:0]) and 32 local streams (L_D[31:0]). Connection memory is physically addressed by time slot (7 bits), H1x0/local select (1 bit), and stream (5 bits). The 8192 locations are divided into four pages of 2048, with each page dedicated to a set of 16 serial streams as follows:
n H1x0 even streams (CT_D[30, 28, . . . 0]) n H1x0 odd streams (CT_D[31, 29, . . . 1]) n Local high streams (L_D[31:16]) n Local low streams (L_D[15:0])
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Each of these connection memory pages are initialized at reset (valid bit entries are reset to invalid). Additionally, each page may be initialized individually via software command, RESET PAGE (refer to Figure 35 on page 136 and Figure 42 on page 141). For standard telephony switching connections, the connection memory locations contain one-half simplex switch control information (refer to Figure 36 on page 137 and Figure 43 on page 141), as follows:
n VALID bit indicates that a valid switch connection exists for this stream/time-slot. n VTC indicates whether the connection is a virtual channel connection or a telephony connection. A 0 denotes a
telephony connection.
n RWS indicates whether the connection is from (from serial stream to data memory) or to (from DATA memory to
serial stream).
n VFC (virtual framing control) controls which data page is used in double-buffer scenarios.
Note: There are three data memory configurations that allow double-buffering of the data, in order to create constant frame delay connections. Refer to Section 14.2.1.2 on page 148 and Section 14.2.2.1 on page 149.
n PME indicates a pattern mode connection. n TAG is the data memory location used for this one-half simplex switch connection (or the data pattern sent to
serial output for pattern mode connections).
n SUBRATE information is subrate switching control (bitswap).
For virtual channel (packet payload) switching connections, there are two possible control fields, depending on whether the virtual channel is nonbonded (refer to Figure 37) or bonded (refer to Figure 38). 14.2.1.1.1 Virtual Channel Switching, Nonbonded Connections
n VALID bit indicates that a valid switch connection exists for this stream/time slot. n VTC indicates whether the connection is a virtual channel connection or a telephony connection. A 1 denotes a
virtual channel connection.
n RWS indicates whether the connection is from (from serial stream to data memory) or to (from DATA memory to
serial stream).
n BVF is bonded virtual frame marker (unused for nonbonded channels). n BCC is bonded channel control indicator; 0 denotes a nonbonded channel. n VC identifier and VCP indicates which virtual channel this information is for (0 up to 511 virtual channels). n SVF (subrate virtual frame marker) is an indicator for the last piece of a packed subrate byte. n SUBRATE information is subrate switching control (bitswap); refer to Section 14.2.2.3.
14.2.1.1.2 Virtual Channel Switching, Bonded Connections
n VALID bit indicates that a valid switch connection exists for this stream/time slot. n VTC indicates whether the connection is a virtual channel connection or a telephony connection. A 1 denotes a
virtual channel connection.
n RWS indicates whether the connection is from (from serial stream to data memory) or to (from data memory to
serial stream).
n BVF (bonded virtual frame marker) is an indicator for the last byte switched in a frame.
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14 Connection Control--Standard and Virtual Channel (continued)
n BCC (bonded channel control indicator), a 1 denotes a bonded channel. n VC identifier and VCP indicates which virtual channel this information is for (0 up to 511 virtual channels). n Bonded channel depth defines how many bytes within one frame are switched. n Bonded channel offset is a specific data memory pointer offset for the data byte related to this connection.
14.2.1.2 Data Memory The T8110 data memory is 4096 bytes, which can be programmatically configured in six ways, via the data memory mode select register (0x00105; refer to Section 6.1.3 on page 48). The data memory is allocated either for 4 Kbytes telephony, 4 Kbytes of virtual channels, or 2 Kbytes of telephony and 2 Kbytes of virtual channels; see Figure 49.
DATA MEMORY MODES 0x20000 DATA MEMORY ADDRESSING 0x20000 4K UTILIZED 0x20FFF 0x21000 0x20800 0x20BFF TEL TEL TEL 0x20FFF 0x20000 TEL 0x207FF 4K SINGLE BUFFERED SWITCH (SET BY CONTROL REGISTER 0x00105)
2K SINGLE BUFFRED + 1K DOUBLE BUFFERED
0x20000 TEL 0x207FF TOTAL ADDRESSED SPACE IS 64K 0x20000 (RESERVED) 0x207FF 0x20800 0x20FFF TEL VC TEL
2K DOUBLE BUFFERED SWITCH
2K SINGLE BUFFERED SWITCH + 2K VIRTUAL CHANNELS
0x20000 0x203FF TEL 0x20800 VC 0x20FFF 0x2FFFF 0x20000 VC 0x20FFF TEL
1K DOUBLE BUFFERED SWITCH + 2K VIRTUAL CHANNELS
4K VIRTUAL CHANNELS
5-9638 (F)
Figure 49. T8110 Data Memory Map and Configurations
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14 Connection Control--Standard and Virtual Channel (continued)
14.2.1.3 Virtual Channel Memory The T8110 virtual channel memory consists of 512 locations, one location for each possible virtual channel. Virtual channel memory consists of two portions, static and scratchpad, and controls how the VC portion of the data memory is partitioned when the data memory is configured to allow for virtual channels (refer to Figure 49). The data memory partition for a virtual channel is defined by the static portion of the virtual channel memory (refer to Figure 39 and Figure 40), which includes the following information:
n SBA (static base address) is the physical start address for this particular virtual channel in the data memory VC
space.
n STD (static depth) is the total number of bytes (in DWORDS) allotted for this virtual channel. A virtual channel
can occupy 2 DWORDS (minimum) up to 64 DWORDS (maximum) in the data memory VC space. The scratchpad portion of the virtual channel memory (refer to Figure 39 and Figure 41) keeps track of the current data memory address within the data memory partition as follows:
n SPCD (scratchpad current depth) is the current number of bytes transferred to/from serial streams. n SPCO (scratchpad current offset) is the data memory address pointer.
14.2.2 Standard Switching Standard telephony switching is achieved by loading control fields into the connection memory for one-half simplex connections (refer to Figure 36 on page 137, Figure 43 on page 141, and Section 14.2.1.1 on page 146). 14.2.2.1 Constant Delay and Minimum Delay Connections The VFC control bit in connection memory determines which of two data pages is accessed, when the data memory is configured to double-buffering for telephony connections (refer to Figure 49). This bit always affects to connections (read the data memory, send it out to a serial stream output) in a double-buffer configuration. This bit can control a from connection in a double-buffer configuration, only if it is a subrate connection; otherwise, the VFC bit has no bearing on from connections. The double-buffering configuration creates two data pages. During a particular frame (125 s time boundary, partitioned into time-slots), one page is the active page, the other is the inactive page. The active/inactive page status toggles at every frame boundary. For all from connections (except for subrate connections), incoming serial data is always written to the active page. For all to connections, the VFC control bit indicates whether to read from the active or inactive page. Manipulation of this bit affects the latency between the incoming from data and the outgoing to data. This latency defines whether or not a connection is constant delay or minimum delay. Please see Appendix A on page 190 for more details on constant and minimum delay connections. 14.2.2.2 Pattern Mode The PME control bit in connection memory affects only to connections. Instead of reading a value out of the data memory for subsequent output to a serial stream, the lower 8 bits of the TAG field provide a byte pattern for the serial output. 14.2.2.3 Subrate The subrate control bit field in connection memory is used only by from connections and controls how individual bits or groups of bits of an incoming serial byte are shuffled prior to writing them to the data memory, in order to achieve subrate switching.
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14.2.2.3.1 Subrate Switching Overview Traditional byte-oriented TDM data switching provides 8 bits of data per time slot, or channel, regardless of the TDM stream bit rate. A particular channel occurs once every 8 kHz frame, and there are 8K frames per second. This allows for a channel data propagation rate of (8 bits/frame * 8K frames/s = 64 Kbits/s). Refer to Figure 50 and Table 113.
ONE FRAME (8 KHz)
8 MBITS/S 4 MBITS/S 2 MBITS/S
0 0
1
2 1 0
3
4 2
5
6 3 1
7
124 62
125
126 63 31
127
TDM Stream Bit TDM STREAM BIT rate = 8MB/s: each stream EACH STREAM HAS RATE = 8 MBITS/S: has 128 TIME SLOTS (CHANNELS) PER FRAME 128 timeslots (channels) per frame
EACH CHANNEL CONTAINS ONE 8-BIT BYTE, REGARDLESS OF THE TDM DATA STREAM BIT RATE
TDM STREAM BIT RATE = 4 MBITS/S: EACH STREAM HAS 64 TIME SLOTS (CHANNELS) PER FRAME TDM STREAM BIT RATE = 2 MBITS/S: EACH STREAM HAS 32 TIME SLOTS (CHANNELS) PER FRAME
Figure 50. TDM Data Stream Bit Rates
Subrate refers to switching fractional portions of the byte-oriented TDM data streams. The T8110 allows the 8 bits of a byte-oriented channel to be broken into multiple channels of fewer bits, either two 4-bit channels, four 2-bit channels, or eight 1-bit channels. This lowers the data propagation rate per channel, but increases the overall channel capacity for a given time-slot. Refer to Table 112 and Table 113. Table 112. TDM Data Stream One Time-Slot (or Channel) Bit Di-Bit Nibble Byte
Notes: Bit subrate = 8 channels per time slot, 1 bit per channel. Di-bit = 4 channels per time slot, 2 bits per channel. Nibble subrate = 2 channels per time slot, 4 bits per channel. Byte (no subrate) = 1 channel per time slot, 8 bits per channel.
.
7 7:6
6
5 5:4 7:4
4
3 3:2
2
1 1:0 3:0
0
7:0
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14 Connection Control--Standard and Virtual Channel (continued)
Table 113. Subrate Switching, Data Propagation Rate vs. Channel Capacity Subrate Type Bit Di-bit Nibble Byte (no subrate) Bits per Channel 1 2 4 8 Channel Data Propagation Rate (Bits/Frame x 8K Frames/s) 8 Kbits/s 16 Kbits/s 32 Kbits/s 64 Kbits/s Channel Capacity (Relative to Byte Switching) 8X 4X 2X 1X
14.2.2.3.2 Subrate Switching Using T8110 The H1x0 bus and the local stream bus are based on byte-oriented TDM data streams--data is always switched as whole bytes. The subrate data must be packed into these bytes prior to switching (refer to Sections 14.2.2.3.3 and 14.2.2.3.4). The data bytes are not necessarily constrained to using fully packed bytes--any portion of a byte may be used. Subrate switching using T8110 requires the following:
n Overall subrate enable mode is activated (register 0x00105, data memory mode select bit 7 is set; see Section
6.1.3 on page 48).
n The subrate field of the connection memory entry for that switch connection is set up. This field contains 7 bits
which control the type of subrate (i.e., bit, di-bit, nibble, or byte), and the data bit shuffling within the TDM byte data, from and to (refer to Figure 36 on page 137, Figure 43 on page 141, and Table 114).
n The VFC connection memory bit for cases where a double-buffering configuration is set up in the data memory
(refer to Figure 36, Figure 43, and Sections 14.2.1.2, 14.2.2.1). In order to program a subrate simplex connection, the subrate field is only required for the from half of that connection. Incoming serial byte data has its bit positions rearranged based on the subrate field contents prior to being written into the data memory. For double-buffered data memory configurations, the VCF bit controls which of two data pages the rearranged byte is written to. The to half of a subrate simplex connection simply outputs the entire byte found at the data memory location used for that connection, and its connection memory subrate field is ignored. Table 114. Subrate Switching, Connection Memory Programming Setup Subrate Type Bit Subrate Connection Memory Bit Field (6:0) 6 1 5 4 3 2 1 0 000 = to bit 0 000 = from bit 0 001 = to bit 1 001 = from bit 1 010 = to bit 2 010 = from bit 2 011 = to bit 3 011 = from bit 3 100 = to bit 4 100 = from bit 4 101 = to bit 5 101 = from bit 5 110 = to bit 6 110 = from bit 6 111 = to bit 7 111 = from bit 7 Subrate Connection Memory Bit Field (6:0) 4 3 2 1 0 Reserved 00 = to bits[1:0] 00 = from bits[1:0] 01 = from bits[3:2] 01 = to bits[3:2] 10 = to bits[5:4] 10 = from bits [5:4] 11 = from bits[7:6] 11 = to bits[7:6]
6 Di-Bit 01
5
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14 Connection Control--Standard and Virtual Channel (continued)
Table 114. Subrate Switching, Connection Memory Programming Setup (continued) Subrate Type Nibble 6 5 001 Subrate Connection Memory Bit Field (6:0) 4 3 2 1 0 = from bits[3:0] Reserved 1 = from bits[7:4] Subrate Connection Memory Bit Field (6:0) 4 3 2 1 Reserved 0 0 = to bits[3:0] 1 = to bits[7:4] 0
6 Byte
5 000
14.2.2.3.3 Subrate Packing of Outgoing Bytes The output from subrate connections is always an entire byte so that it does not violate the H.100 or H.110 specifications. The output byte is composed of smaller, i.e., subrate pieces. The process of combining the incoming pieces into a whole byte suitable for output is called packing. In the T8110 (and other subrate-capable Ambassador devices), packing is accomplished by making several from connections for each single to connection. For example, in Figure 48, four from connections (of different stream/time-slot origins), all di-bits, are used to construct a byte that will be output as defined by the to connection. The outgoing to half of a simplex connection reads an entire byte from a data memory location. The packing of separate incoming subrate pieces into this byte is achieved by setting up multiple from one-half simplex connections for one to one-half simplex connection, all using the same data memory location. An example is illustrated in Figure 48. This example shows the packing of four separate incoming di-bits from four different channels into one outgoing byte on one channel. Note: Please note the limitation that multiple di-bits from the same time slot cannot be switched simultaneously. This would require the byte of that time slot to be unpacked first, which is discussed in Section 14.2.2.3.4 on page 153.
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FRAME (8 KHz)
TIMESLOT
TIMESLOT BIT POSTITIONS OF DI-BITS WITHIN THE DATA BYTE STREAM a, DI-BIT CHANNELS IN STREAM b, DI-BIT CHANNELS IN STREAM c, DI-BIT CHANNELS IN STREAM d, DI-BIT CHANNELS IN
7: 6 5: 4
n
3: 2 1: 0 7: 6
n+1
5: 4 3: 2 1: 0 7: 6
n+2
5: 4 3: 2 1: 0 7: 6
n+3
5: 4 3: 2 1: 0 7: 6
n + 10
5: 4 3: 2 1: 0
a 1
a 2
a 3
a 4 b 1 b 2 b 3 b 4 c 1 c 2 c 3 c 4 d 1 d 2 d 3 d 4 a 4 d 2 b 4 c 3
STREAM e, DI-BIT CHANNELS OUT
Notes: Connectivity is as follows:
n n n n
From stream a, time slot n, bits[1:0] to stream e, time slot n + 10, bits[7:6]. From stream b, time slot n + 1, bits[1:0] to stream e, time slot n + 10, bits[3:2]. From stream c, time slot n + 2, bits[3:2] to stream e, time slot n + 10, bits[1:0]. From stream d, time slot n + 3, bits[5:4] to stream e, time slot n + 10, bits[5:4].
Required connection memory programming is as follows: Five 1/2 simplex connections are required to pack four incoming di-bits into an outgoing byte.
n n n n n
From stream a, time slot n. Connection memory subrate field = 0100X11. From stream b, time slot n + 1. Connection memory subrate field = 0100X01. From stream c, time slot n + 2. Connection memory subrate field = 0101X00. From stream d, time slot n + 3. Connection memory subrate field = 0110X10. To stream e, time slot n + 10. Connection memory subrate field is don't care.
Figure 51. Subrate Switching Example, Byte Packing
14.2.2.3.4 Subrate Unpacking of Incoming Bytes Because the H1x0 bus and the local stream bus are based on byte-oriented TDM data streams, and the T8110 architecture is geared towards standard byte switching, it is not possible to simultaneously switch subrate portions of a single byte to different places. This limitation is overcome by application. To gain access to each subrate piece contained in one incoming byte, that byte must be broadcast onto additional channels, one channel for each subrate piece required. The means of broadcasting is up to the application--either the source device of the packed subrate byte can broadcast it, or the device receiving that byte can broadcast it over unused channels and loop the broadcast bytes back in. The example from Figure 51 is extended in Figure 52. This example shows the unpacking of the packed byte created in Figure 51, output to four different channels.
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FRAME (8 KHz)
TIMESLOT
TIMESLOT BIT POSTITIONS OF DI-BITS WITHIN THE DATA BYTE
7: 6
n+3
5: 4 3: 2 1: 0 7: 6
n+4
5: 4 3: 2 1: 0 7: 6
n+5
5: 4 3: 2 1: 0 7: 6
n+6
5: 4 3: 2 1: 0 7: 6
n+7
5: 4 3: 2 1: 0 7: 6
n+8
5: 4 3: 2 1: 0
BROADCASTED INCOMING BYTE STREAM e, DI-BIT CHANNELS IN a 4 d 2 b 4 c 3 a 4 d 2 b 4 c 3 a 4 d 2 b 4 c 3 a 4 d 2 b 4 c 3
STREAM f, DI-BIT CHANNELS IN (BROADCASTS OF THE ORIGINAL INPUT)
STREAM g, DI-BIT CHANNELS OUT STREAM h, DI-BIT CHANNELS OUT STREAM i, DI-BIT CHANNELS OUT STREAM j, DI-BIT CHANNELS OUT
a 4
X
XX X d 2
XX X c 3 b 4 X
XX XX
Notes: Connectivity is as follows: From stream e, time slot n + 3, bits[1:0] to stream j, time slot n + 8, bits[7:6]. From stream f, time slot n + 5, bits[3:2] to stream i, time slot n + 8, bits[5:4]. From stream f, time slot n + 6, bits[5:4] to stream h, time slot n + 8, bits[1:0]. From stream f, time slot n + 7, bits[7:6] to stream g, time slot n + 8, bits[7:6]. Required connection memory programming is as follows: Eight 1/2 simplex connections are required to unpack one incoming byte to four separate outgoing di-bits. From stream e, time slot n + 3. Connection memory subrate field = 0100X11. From stream f, time slot n + 5. Connection memory subrate field = 0101X10. From stream f, time slot n + 6. Connection memory subrate field = 0110X00. From stream f, time slot n + 7. Connection memory subrate field = 0111X11. To stream g, time slot n + 8. Connection memory subrate field is don't care. To stream h, time slot n + 8. Connection memory subrate field is don't care. To stream i, time slot n + 8. Connection memory subrate field is don't care. To stream j, time slot n + 8. Connection memory subrate field is don't care.
Figure 52. Subrate Switching Example, Byte Unpacking
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14 Connection Control--Standard and Virtual Channel (continued)
14.2.3 Virtual Channel (Packet Payload) Switching Packet payload switching is achieved by loading control fields into the connection memory for one-half simplex connections (refer to Figure 37 and Figure 38) and loading control fields for a corresponding virtual channel into the virtual channel memory (refer to Figure 39--Figure 41). A virtual channel connection consists of the following two parts:
n A one-half simplex connection to (or from) a channel (or channels) in the H1x0 or local bus TDM switching
domain. These connections are made in a similar manner to standard telephony switching connections--by loading the proper control fields into the T8110 connection memory (refer to Section 14.2.1.1, Figure 38, and Figure 39). There are two types of virtual channel connections: nonbonded refers to switching of a single TDM channel each frame, bonded refers to switching of multiple TDM channels each frame. Additionally, subrate switching is allowed for nonbonded virtual channels. Refer to Sections 14.2.3.1--14.2.3.3 for more details.
n A store-and-forward buffer that has access from (or to) an external buffer which is defined somewhere in the
PCI bus space (see Section 14.2.3.4). The T8110 uses its data memory as the store-and-forward buffer. Depending on the data memory configuration (refer to Figure 49), there can be as many as 512 unique virtual channels defined simultaneously (using all 4 Kbytes of the available space). Configuration of the data memory space for virtual channels is achieved by loading control fields into the virtual channel memory (refer to Section 14.2.1.2, 14.2.1.3, and Figure 39--Figure 41). The above two parts define a virtual channel. Each virtual channel can be either:
n From TDM domain to PCI domain. The data flow from incoming serial TDM data to the PCI external buffer is
referred to as PUSH. In this case, the T8110 controls writes to the external buffer. Another agent on the PCI bus (such as a coprocessor) would control the reads from the external buffer. The handshake between the T8110 and the other agent is described in Section 14.2.3.4.
n From PCI domain to TDM domain. The data flow from the PCI external buffer to outgoing serial TDM data is
referred to as PULL. In this case, the T8110 controls reads from the external buffer. Another agent on the PCI bus (such as a coprocessor) would control the writes to the external buffer. The handshake between the T8110 and the other agent is described in Section 14.2.3.4. 14.2.3.1 Nonbonded Channels A nonbonded virtual channel means that only one byte of information per 8 kHz frame is switched in the TDM domain for that channel. The T8110 data memory configuration for any virtual channel holds multiple data bytes at a time (minimum of 8 bytes, maximum of 256 bytes, in increments of 4 bytes). Since only 1 byte per frame is switched, the data memory depth defined for a nonbonded virtual channel directly corresponds to the number of TDM frames worth of data stored at one time. The concept is illustrated in Figure 53 and in Figure 54.
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14 Connection Control--Standard and Virtual Channel (continued)
OVERALL CHANNEL DEPTH = 8 BYTES, 8 FRAMES AT 1 BYTE PER FRAME, BYTE COMES FROM SERIAL STREAM INPUT CT_D2, TIMESLOT 30
FRAME
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
... ...
SCRATCHPAD BASE ADDRESS OFFSET (UPDATED JUST AFTER TIMESLOT 30 OF EACH FRAME)
0
1
2
3
4
5
6
7
0
1
VIRTUAL CHANNEL MEMORY SCRATCHPAD IS IN ITS INITIAL STATE HERE FOR THIS CHANNEL.
AFTER 8 FRAMES AT 1 BYTE PER FRAME, 8 BYTES HAVE BEEN WRITTEN TO THE DATA MEMORY (IT IS FULL). CURRENT DEPTH = OVERALL CHANNEL DEPTH = 8. NOTIFY THE PACKET SWITCH CIRCUIT TO PUSH THE DATA OUT OF THE DATA MEMORY TO THE EXTERNAL BUFFER, AND RESET THE VIRTUAL CHANNEL MEMORY SCRATCHPAD TO ITS INITIAL STATE FOR THIS CHANNEL.
TIMESLOT
0
1
...
30
...
126
127
INCREMENT THE SCRATCHPAD CURRENT DEPTH COUNTER, WRITE A BYTE FROM SERIAL STREAM INPUT TO DATA MEMORY: ADDRESS = (STATIC BASE ADDRESS + SCRATCHPAD BASE ADDRESS OFFSET)
Figure 53. Nonbonded Virtual Channel in the PUSH Direction
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14 Connection Control--Standard and Virtual Channel (continued)
OVERALL CHANNEL DEPTH = 8 BYTES, 8 FRAMES AT 1 BYTE PER FRAME, BYTE GOES TO SERIAL STREAM OUTPUT CT_D3, TIMESLOT 50 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9
FRAME SCRATCHPAD BASE ADDRESS OFFSET (UPDATED JUST BEFORE TIMESLOT 50 OF EACH FRAME)
... ...
0
1
2
3
4
5
6
7
0
1
VIRTUAL CHANNEL MEMORY SCRATCHPAD IS IN ITS INITIAL STATE HERE FOR THIS CHANNEL.
AFTER 8 FRAMES AT 1 BYTE PER FRAME, 8 BYTES HAVE BEEN READ FROM THE DATA MEMORY (IT IS EMPTY). CURRENT DEPTH = OVERALL CHANNEL DEPTH = 8. NOTIFY THE PACKET SWITCH CIRCUIT TO PULL FRESH DATA FROM THE EXTERNAL BUFFER INTO DATA MEMORY, AND RESET THE VIRTUAL CHANNEL MEMORY SCRATCHPAD TO ITS INITIAL STATE FOR THIS CHANNEL.
TIMESLOT
0
1
...
50
...
126
127
INCREMENT THE SCRATCHPAD CURRENT DEPTH COUNTER, READ A BYTE FROM DATA MEMORY TO SERIAL STREAM OUTPUT: ADDRESS = (STATIC BASE ADDRESS + SCRATCHPAD BASE ADDRESS OFFSET)
Figure 54. Nonbonded Virtual Channel in the PULL Direction
14.2.3.2 Subrate Nonbonded virtual channels in the PUSH direction allow for subrate switching and the packing of incoming subrate pieces into bytes. (Refer to Section 14.2.2.3 for a general description of subrate. For the PULL direction, all bits of the byte are output to the TDM domain so subrate is not applicable.) In addition to the normal subrate field loaded into the connection memory (refer to Table 114), one additional control bit, SVF subrate virtual frame marker (refer to Section 14.2.1.1), is required as a means to denote the completion of a byte packing operation. Please refer to Figure 55.
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Data Sheet May 2001
14 Connection Control--Standard and Virtual Channel (continued)
OVERALL CHANNEL DEPTH = 8 BYTES, 8 FRAMES AT 1 BYTE PER FRAME, BYTE COMES FROM GATHERING DI-BITS FROM VARIOUS TIMESLOTS OF CT_D4 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9
FRAME
... ...
SCRATCHPAD BASE ADDRESS OFFSET (UPDATED JUST AFTER TIMESLOT 64 OF EACH FRAME)
0
1
2
3
4
5
6
7
0
1
VIRTUAL CHANNEL MEMORY SCRATCHPAD IS IN ITS INITIAL STATE HERE FOR THIS CHANNEL.
AFTER 8 FRAMES AT 1 BYTE PER FRAME, 8 BYTES HAVE BEEN WRITTEN TO THE DATA MEMORY (IT IS FULL). CURRENT DEPTH = OVERALL CHANNEL DEPTH = 8 NOTIFY THE PACKET SWITCH CIRCUIT TO PUSH THE DATA OUT OF THE DATA MEMORY TO THE EXTERNAL BUFFER, AND RESET THE VIRTUAL CHANNEL MEMORY SCRATCHPAD TO ITS INITIAL STATE FOR THIS CHANNEL.
TIMESLOT
0
1
...
10
...
12
...
23
...
64
...
126
127
CONNECTION MEMORY SFV SUBRATE VIRTUAL FRAME FOR CT_D4, TIMESLOT X SVF IS ACTIVE, UPDATE SCRATCHPAD: BASE ADDRESS OFFSET = (BASE ADDRESS OFFSET +1) WRITE A DI-BIT FROM SERIAL STREAM INPUT TO DATA MEMORY: ADDRESS = (STATIC BASE ADDRESS + SCRATCHPAD BASE ADDRESS OFFSET)
WRITE THE FINAL DI-BIT FROM SERIAL STREAM INPUT TO DATA MEMORY: ADDRESS = (STATIC BASE ADDRESS + SCRATCHPAD BASE ADDRESS OFFSET)
Figure 55. Nonbonded Virtual Channel with Subrate and Packed Bytes
14.2.3.3 Bonded Channels A bonded virtual channel means that more than 1 byte of information per 8 kHz frame is switched in the TDM domain for that channel. The number of TDM frames worth of data stored at one time in the T8110 data memory depends on the number of bytes switched per frame, plus the overall data memory depth defined for that channel. For example, if a virtual channel is defined to switch 8 bytes per frame, and the data memory depth is set to 128 bytes, then the data memory for that channel can store 16 TDM frames worth of data at a time. An additional control bit, BVF (bonded virtual frame marker; refer to Section 14.2.1.1), is required as a means to mark the last byte switched in a frame. The concept is illustrated in Figure 56 and in Figure 57.
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
14 Connection Control--Standard and Virtual Channel (continued)
OVERALL CHANNEL DEPTH = 128 BYTES, 16 FRAMES AT 8 BYTES PER FRAME, BYTES COME FROM SERIAL STREAM INPUT CT_D0, TIMESLOTS 20 TO 27
FRAME SCRATCHPAD BASE ADDRESS OFFSET (UPDATED JUST AFTER TIMESLOT 27 OF EACH FRAME)
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
...
0
8
16
24
32
40
48
56
64
72
80
88
96
104
112
120
0
8
...
VIRTUAL CHANNEL MEMORY SCRATCHPAD IS IN ITS INITIAL STATE HERE FOR THIS CHANNEL.
AFTER 16 FRAMES AT 8 BYTES PER FRAME, 128 BYTES HAVE BEEN WRITTEN TO THE DATA MEMORY (IT IS FULL). CURRENT DEPTH = OVERALL CHANNEL DEPTH = 128. NOTIFY THE PACKET SWITCH CIRCUIT TO PUSH THE DATA OUT OF THE DATA MEMORY TO THE EXTERNAL BUFFER, AND RESET THE VIRTUAL CHANNEL MEMORY SCRATCHPAD TO ITS INITIAL STATE FOR THIS CHANNEL.
TIMESLOT CONNECTION MEMORY BONDED CHANNEL OFFSET FOR CT_D0, TIMESLOT X CONNECTION MEMORY BVF VIRTUAL FRAME MARKER FOR CT_D0, TIMESLOT X
0
1
...
20
21
22
23
24
25
26
27
...
7
126
127
0
1
2
3
4
5
6
WRITES TO MEMORY ARE ONE TIMESLOT LOOKBEHIND
BVF IS ACTIVE, UPDATE SCRATCHPAD: BASE ADDRESS OFFSET = (BASE ADDRESS OFFSET + CONNECTION MEMORY BONDED CHANNEL DEPTH)
INCREMENT THE SCRATCHPAD CURRENT DEPTH COUNTER, WRITE A BYTE FROM SERIAL STREAM INPUT TO DATA MEMORY: ADDRESS = (STATIC BASE ADDRESS + SCRATCHPAD BASE ADDRESS OFFSET + CONNECTION MEMORY BONDED CHANNEL OFFSET)
Figure 56. Bonded Virtual Channel in the PUSH Direction
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14 Connection Control--Standard and Virtual Channel (continued)
OVERALL CHANNEL DEPTH = 128 BYTES, 16 FRAMES AT 8 BYTES PER FRAME, BYTES GO TO SERIAL STREAM OUTPUT CT_D1, TIMESLOTS 46 to 53
FRAME
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
...
SCRATCHPAD BASE ADDRESS OFFSET (UPDATED JUST BEFORE TIMESLOT 53 OF EACH FRAME)
0
8
16
24
32
40
48
56
64
72
80
88
96
104
112
120
0
8
...
VIRTUAL CHANNEL MEMORY SCRATCHPAD IS IN ITS INITIAL STATE HERE FOR THIS CHANNEL.
AFTER 16 FRAMES AT 8 BYTES PER FRAME, 128 BYTES HAVE BEEN READ FROM THE DATA MEMORY (IT IS EMPTY). CURRENT DEPTH = OVERALL CHANNEL DEPTH = 128. NOTIFY THE PACKET SWITCH CIRCUIT TO PULL FRESH DATA FROM THE EXTERNAL BUFFER INTO THE DATA MEMORY, AND RESET THE VIRTUAL CHANNEL MEMORY SCRATCHPAD TO ITS INITIAL STATE FOR THIS CHANNEL.
TIMESLOT CONNECTION MEMORY BONDED CHANNEL OFFSET FOR CT_D0, TIMESLOT X CONNECTION MEMORY BVF VIRTUAL FRAME MARKER FOR CT_D0, TIMESLOT X
0
1
...
0
46
47
48
49
50
51
52
53
...
126
127
1
2
3
4
5
6
7 READS FROM MEMORY ARE ONE TIMESLOT LOOKAHEAD
BVF IS ACTIVE, UPDATE SCRATCHPAD: BASE ADDRESS OFFSET = (BASE ADDRESS OFFSET + CONNECTION MEMORY BONDED CHANNEL DEPTH)
INCREMENT THE SCRATCHPAD DEPTH COUNTER, READ A BYTE FROM DATA MEMORY TO SERIAL STREAM OUTPUT: ADDRESS = (STATIC BASE ADDRESS + SCRATCHPAD BASE ADDRESS OFFSET + CONNECTION MEMORY BONDED CHANNEL OFFSET)
Figure 57. Bonded Virtual Channel in the PULL Direction
14.2.3.4 External Buffer Access 14.2.3.4.1 Overview The T8110's general operation is to gather TDM serial stream data in small internal buffers, which are programmable on a per-channel basis (i.e., virtual channels), and then when full, burst the data to a larger external buffer where a corresponding PCI bus agent (such as a coprocessor) can operate on the larger buffers. For purposes of further discussion, the other PCI bus agent will be referred to as the USER. The T8110's onboard storage is 4096 bytes total. For complete usage, this can be defined from as many as 512 buffers of 8 bytes each, to as few as 16 buffers of 256 bytes each, or any combinations that adhere to the following:
n The total allotment does not exceed 4096 bytes. n The T8110 internal buffer sizes are defined in multiples of DWORDS, from 2 DWORDS (minimum) to
64 DWORDS (maximum).
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14 Connection Control--Standard and Virtual Channel (continued)
For a virtual channel in the push direction, the T8110 fills its internal buffer with incoming TDM serial stream data. Once the internal buffer for that channel is full, the T8110 initiates a burst transfer of that data to the external buffer. For a virtual channel in the pull direction, the T8110 empties its internal buffer to outgoing TDM serial stream data. Once the internal buffer for that channel is empty, the T8110 initiates a burst transfer to fetch more data from the external buffer. 14.2.3.4.2 Descriptor Table The first portion of a T8110-initiated transfer is to fetch control information associated with a particular virtual channel. The third portion is an update of that control information, with the transfer of data to/from the external buffer in between; see Section 4.2.2 on page 32 and to Figure 13 on page 33. The control information is stored in a descriptor table, which exists in the PCI bus address space and is accessible by both the T8110 and the USER. The T8110 must have access to the descriptor table's base address, which must be loaded into T8110 registers 0x00110--113 prior to any virtual channel activity. There is one entry in the descriptor table for each of the possible 512 virtual channels. Each entry consists of 8 bytes (2 DWORDS). The maximum space required for the descriptor table is (512 * 8) = 4 Kbytes. A descriptor table entry contains the following information. Table 115. Descriptor Table DWORD First DWORD Second DWORD SOL EE U F Bits[31:24] Bits[23:16] Bits[15:8] Bits[7:0] External buffer last address GBS [2:0] T F TOR[11:0]
External buffer base address UOR[11:0]
n External buffer base address. This is the base address where the external buffer space for this particular virtual
channel begins. Note that only bits [31:12] are defined, which means the external buffer space for a virtual channel is addressed on 4 Kbyte boundaries in the PCI space. This region is read-only for T8110, read-write for the USER.
n External buffer last address. This is the last address offset in the external buffer space for this particular virtual
channel (DWORD-aligned). This region is read-only for T8110, read-write for the USER.
n Control flags. All flags are read-only for T8110, read-write for the USER:
-- SE, stop enable. This determines whether the external buffer is treated as circular for this virtual channel (refer to Section 14.2.3.4.4). 0 = buffer is circular (T8110 can roll over at end-of-buffer), 1 = the buffer is not circular (T8110 must stop at end of buffer). -- OE, overwrite enable. This determines whether the T8110 can overwrite unread data in the external buffer for this virtual channel (refer to Section 14.2.3.4.4). 0 = overwrite is disabled, 1 = overwrite is enabled. -- L, lock. This determines whether the T8110 is allowed access to the external buffer for this virtual channel. 0 = not locked, 1 = locked.
n UF. Toggled by the USER whenever the UOR pointer rolls over at the end of the external buffer. Read-only for
the T8110.
n UOR. This is a USER-updated offset pointer within the defined 4K external buffer space for this virtual channel.
Read-only for the T8110.
n GBS (status). This is supplemental information on the status of the external buffer for this virtual channel (refer to
Section 14.2.3.4.4). These flags are read-write for both the T8110 and the USER. Refer to Table 116.
n TF. Toggled by the T8110 whenever the TOR pointer rolls over at the end of the external buffer. Read-write for
both the T8110 and the USER.
n TOR. T8110 updated offset pointer within the defined 4K external buffer space for this virtual channel. Readwrite for both the T8110 and the USER.
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14 Connection Control--Standard and Virtual Channel (continued)
Table 116. Descriptor Table GBS Status Descriptions GBS Value 000 001 010 011 100 101 110 111 14.2.3.4.3 External Buffer Each virtual channel has an allotment of external buffer space. The external buffer for a virtual channel can be thought of as a FIFO, with the T8110 controlling one side, and the USER controlling the other. The base address and the last address offset of the external buffer is stored in the descriptor table (first DWORD of the entry for the corresponding virtual channel; see previous section). Each external buffer is defined as 4 Kbytes, with the base address at 4 Kbyte boundaries. An external buffer is not limited to exactly 4 Kbytes--it can be smaller or larger, which requires special on-the-fly manipulation of the descriptor table by the USER side (refer to Section 14.2.3.4.4). The only basic requirement for the external buffer size is that it be an integral multiple of the T8110 internal buffer size for a given virtual channel. 14.2.3.4.4 Transfer Protocol The transfer mechanism between the T8110 and the USER is three T8110-initiated PCI transfers: descriptor table fetch, external buffer data transfer, and descriptor table update (refer to Figure 12 and Figure 13). The second transfer (external buffer data transfer) would normally occur; however, it may not occur if the state of the descriptor table control and status flags shows the external buffer not accessible by the T8110. 14.2.3.4.4.1 Descriptor Table Fetch T8110 uses the descriptor table base address stored in its control register field (address 0x00110--113), and adds an address offset determined by which of the possible 512 virtual channels initiated the action to create the descriptor table address for that channel. The transfer is a PCI memory read burst of 2 DWORDS. The descriptor table contents are decoded, and a number of calculations are performed on the descriptor table data. The results of these calculations determine the sequence of further PCI transfers (i.e., whether or not to skip the second external buffer data transfer, and what value(s) to update the descriptor table with). Refer to Figure 58 and Table 116. Status Description USER has initialized the external buffer. T8110 has completed with normal status. T8110 has completed with a boundary condition. T8110 has overwritten a portion of the external buffer unread by USER. USER has initialized the T8110 pointer (TF and TOR). T8110 did not complete due to a locked buffer. T8110 did not complete due to stalled buffer (boundary condition). USER has disabled the external buffer.
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14 Connection Control--Standard and Virtual Channel (continued)
DESCRIPTOR TABLE FETCH
GBS = 111 ?
N
L=1 ?
N
GBS = 010 or 110
N
Y
Y
Y: previous T8110 cycle STALLED
OE = 1 ? Y N Y
UOR updated ? External Buffer is diabled by USER: no T8110 access allowed, assert LOCK ERROR External Buffer is LOCKED by USER: set GBS = 101, assert LOCK ERROR Overwrite is enabled by USER: update external buffer, set GBS = 011, assert OVERWRITE WARNING
N Calculate Boundary Condition
OK RESULT ? OK: update external buffer, update GBS accordingly (001, or'010 and assert STALL WARNING)
INIT condition
ERROR condition
EXTERNAL BUFFER DATA TRANSFER
USER hasn't responded to a T8110 STALL, assert STALL ERROR Boundary ERROR: assert STALL ERROR UOR=TOR for PULL channel: assert INIT WARNING
DESCRIPTOR TABLE UPDATE
Figure 58. Descriptor Table Fetch Decode
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14 Connection Control--Standard and Virtual Channel (continued)
14.2.3.4.5 External Buffer Data Transfer After the descriptor table fetch, the T8110 then does the following:
n It either dumps its internal buffer of gathered TDM data to the external buffer space (push, a PCI memory write
burst of internal buffer size)
n Or fetches data from the external buffer space into its internal buffer for outgoing TDM data (pull, a PCI memory
read burst of internal buffer size).
n Or skips the external buffer data transfer (based on descriptor table status, such as a pointer stall, end-of-buffer
stall, buffer locked status, which indicate that the external buffer is not currently available to the T8110). 14.2.3.4.6 Descriptor Table Update The T8110 then updates the descriptor table (second DWORD only), with values calculated based on the descriptor table fetch results. The only allowable portions writable by T8110 include the GBS status, TF, and TOR. The transfer is a PCI memory write of 1 DWORD. 14.2.3.5 T8110 Packet Switching, Circuit Operation Each programmed T8110 virtual channel operates independently, and tracks both its current position in the T8110 internal buffer space and the buffer full (push) or empty (pull) status, in the scratchpad portion of the virtual channel memory (refer to Section 14.2.1.3). Upon determination of a full (or empty) internal buffer, that channel places an entry into a notify queue and sets a bit in the notify pending memory. Entries in the notify queue get translated into the T8110-initiated external buffer transfer protocol (refer to Section 14.2.3.4.4). Upon completion of that transfer protocol, the notify pending memory bit for that channel is reset.
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14 Connection Control--Standard and Virtual Channel (continued)
14.2.3.5.1 System Errors Due to Packet Switching The system error indicators for packet switch activity are located in the system error register, 0x00126. These indicators are inputs to the interrupt controller, and are maskable interrupts. There are eight indicators, as shown below. Table 117. System Error Register Address 0x00126 BIT 7 Mnemonic PMFOB Description PCI master, fatal error--this bit is set when a T8110-initiated PCI cycle results in abnormal termination, including the following: n Requested PCI target does not respond (master abort).
n Requested PCI target terminates (target abort). n Requested PCI target responds with PCI_DEVSEL#, but does not follow with
PCI_TRDY# or PCI_STOP# to allow the cycle to complete (PCI_TRDY# time-out, see Table 12 on page 34).
n Requested PCI target retries beyond the retry count (RETRY time-out, see Table 12 on
page 34). 6 PMLOB PCI master, external buffer LOCK error--this bit is set when a T8110 descriptor table fetch indicates the USER has locked the external buffer, and T8110 access to the external buffer is denied. PCI master, external buffer STALL error--this bit is set when a T8110 descriptor table fetch indicates that there is a pointer boundary condition (end-of-buffer, or T8110 pointer has caught up to USER pointer), and T8110 access to the external buffer is denied. PCI master, external buffer STALL error--this bit is set when a T8110 descriptor table fetch indicates that there is only one external buffer access left before a pointer boundary condition (end-of-buffer, or T8110 pointer has caught up to USER pointer). T8110 access to the external buffer is allowed. PCI master, external buffer OVERWRITE warning--this bit is set when a T8110 descriptor table fetch indicates the USER has enabled the T8110 to overwrite unread data in the external buffer (i.e., override a boundary condition). This is applicable for push operation only. PCI master, external buffer INITIAL warning--this bit is set when a T8110 descriptor table fetch indicates the USER has not written anything into the external buffer (the initial state of a pull operation). Virtual channel memory, scratchpad OVERFLOW warning--indicates the calculated scratchpad current depth has exceeded the overall buffer depth (VC programming error). NOTIFY_QUEUE OVERFLOW warning--indicates that a request to push (or pull) a packet of data did not occur within one frame time (125 us), and T8110's internal data buffer will get overwritten (push) or contain stale data (pull).
5
PMEOB
4
PMWOB
3
PMOOB
2
PMIOB
1 0
VCOOB NQOOB
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15 Electrical Characteristics
15.1 Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage; the table below shows absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 118. Absolute Maximum Ratings Parameter Supply Voltage XTAL1_IN, XTAL2_IN, XTAL1_OUT, XTAL2_OUT pins Voltage Applied to I/O Pins Operating Temperature Storage Temperature 15.1.1 Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Agere employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500 W, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The T8110 has a HBM ESD threshold voltage rating of 1500 V minimum. Symbol VDD -- -- -- Tstg Min -- VSS VSS - 0.3 -40 -55 Max 4.2 VDD VDD 5.5 85 125 Unit V V V C C
15.2 Crystal Specifications
15.2.1 XTAL1 Crystal The T8110 requires a 16.384 MHz clock source derived from an oscillator or a crystal. If a crystal is used it has to be a 16.384 MHz crystal and must be connected between the XTAL1_IN and the XTAL1_OUT pins. External 24 pF, 5% capacitors must be connected from XTAL1_IN and XTAL1_OUT to Vss, as shown in the diagram below. The 32 ppm tolerance is the suggested value if the oscillator is used as the clocking source while mastering the bus. Otherwise, a crystal with a lesser tolerance can be used. The crystal specifications are shown below. Table 119. XTAL1 Specifications Parameter Frequency Oscillation Mode Effective Series Resistance Load Capacitance Shunt Capacitance Frequency Tolerance and Stability Value 16.384 MHz Fundamental, parallel resonance 50 maximum 18 pF 7 pF maximum 32 ppm
XTAL1_OUT T8110 1 M 24 pF XTAL1_IN 16.384 MHZ CRYSTAL VSS
5-6390f(c)
24 pF
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15 Electrical Characteristics (continued)
If an oscillator is used (see Section 7.4.4 on page 79), the signal has to be connected to the XTAL1_IN pin. XTAL1_OUT must be left unconnected in this configuration. XTAL1_IN and XTAL1_OUT are not 5 V tolerant. The oscillator must meet the requirements shown below. Table 120. 16.384 MHz Oscillator Requirements Parameter Frequency Maximum Rise or Fall Time Minimum Pulse Width Low 20 ns 15.2.2 XTAL2 Crystal XTAL2 is an optional crystal oscillator input. If a crystal is used, it has to be a 6.176 MHz or a 12.352 MHz crystal and must be connected between the XTAL2_IN and the XTAL2_OUT pins, as shown in the diagram below. External 24 pF, 5% capacitors must be connected from XTAL2_IN and XTAL2_OUT to Vss. The 32 ppm tolerance is the suggested value if the oscillator is used as the clocking source while mastering the bus. Otherwise, a crystal with a lesser tolerance can be used (see Table 121). If XTAL2 is not used, XTAL2_IN should be tied to VDD and XTAL2_OUT should be left unconnected. Table 121. XTAL2 Specifications Parameter Frequency Oscillation Mode Effective Series Resistance Load Capacitance Shunt Capacitance Frequency Tolerance and Stability
* 120 maximum for 6.176 MHz crystal. 24 pF for 6.176 MHz crystal also. 18 pF for 6.176 MHz crystal also.
Value 16.384 MHz 10 ns, 10%--90% VDD High 20 ns
Value 12.352 MHz Fundamental, parallel resonance 75* maximum 18 pF 7 pF maximum 32 ppm
5-6390d
XTAL2_OUT 24 pF T8110 XTAL2_IN 1 M 24 pF 12.352 MHz CRYSTAL VSS
If an oscillator is used (see Section 7.5.1 on page 81), the signal has to be connected to the XTAL2_IN pin. XTAL2_OUT must be left unconnected in this configuration. XTAL2_IN and XTAL2_OUT are not 5 V tolerant. The oscillator must meet the requirements shown below. Table 122. 6.176 MHz/12.352 MHz Oscillator Requirements Parameter Frequency Maximum Rise or Fall Time Minimum Pulse Width Low 54 ns Value 6.176 MHz 10 ns, 10%--90% VDD High 54 ns Value 12.352 MHz 10 ns, 10%--90% VDD Low 27 ns High 27 ns
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15 Electrical Characteristics (continued)
15.2.3 Reset Pulse Table 123. Reset Pulse Parameter RESET# Minimum Pulse Width Min 61 Max -- Unit ns
15.3 Thermal Considerations for the 272 PBGA
Table 124. Thermal Considerations Parameter Body Size (mm sq.) Array Details Ball Pitch (mm) Number of Layers Theta-JA (C/W) Natural 200 fpm convection 22.5 19 500 fpm 17.5 2.44 Maximum Power (Natural Convection) (Watts)
4-layer JEDEC Test Board
27
Peripheral + T.A.
1.27
2
15.4 dc Electrical Characteristics
15.4.1 PCI Signals All PCI signals meet the electrical requirements as specified in the PCI Local Bus, Rev 2.2, specification. PCI interface timing diagrams can be found in Figure 6--Figure 15, starting on page 25.
15.4.2 Electrical Drive Specifications, CT_C8 and /CT_FRAME VDD = 3.3 V and VSS = 0.0 V, unless otherwise specified. Table 125. Electrical Drive Specifications, CT_C8 and /CT_FRAME Parameter Output High Voltage Output Low Voltage Positive-going Threshold Negative-going Threshold Hysteresis (Vt+--Vt-) Input Pin Capacitance Symbol VOH VOL Vt+ Vt- VHYS CIN Condition IOUT = -24 mA IOUT = 24 mA -- -- -- -- Min 2.4 -0.25 1.2 0.6 0.4 -- Max 3.3 0.4 2.0 1.6 -- 10 Unit V V V V V pF
PCI-compliant data line I/O cells are used for the CT bus data lines. (See PCI Specification, Rev. 2.2, Chapter 4.) /C16, /C4, C2, SCLK, /SCLKx2, and /FR_COMP all use the same driver/receiver pairs as those specified for the CT_C8 and /CT_FRAME signals, though this is not explicitly stated as a part of the H.1x0 specification.
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15 Electrical Characteristics (continued)
15.4.3 All Other Pins VDD = 3.3 V and Vss = 0.0 V, unless otherwise specified. Table 126. dc Electrical Characteristics, All Other Pins Parameter Supply Current Supply Voltage Input High Voltage Input Low Voltage Input Current Input Capacitance (input only) Input Capacitance (I/O pins) Leakage Current (3-state) Input Clamp Voltage Output High Voltage Output Low Voltage Output Short-circuit Current Symbol IDD VDD VIH VIL II CI CIO ILEAK VC VOH VOL IOS Condition 2000 H-bus/L-bus connections -- -- -- -- -- -- -- -- I = 8 mA I = 8 mA VOH tied to GND Min -- 3.0 2.0 -- -- -- -- -- -- 2.4 -- -- Typ 300 -- -- -- -- -- -- -- -- -- -- -- Max -- 3.6 -- 0.8 1 5 10 10 -1.0 -- 0.4 100 Unit mA V V V A pF pF A V V V mA
15.5 H-Bus Timing
15.5.1 Timing Diagrams
FRAME BOUNDARY
/CT_FRAME (A/B) CT_C8 (A/B) /FR_COMP /C16 C2 /C4 SCLK (2.048 MHz) /SCLKx2 (2.048 MHz MODE) SCLK (4.096 MHz MODE) /SCLKx2 (4.096 MHz MODE) SCLK (8.192 MHz MODE) /SCLKx2 (8.192 MHz MODE)
5-6119F
Figure 59. Clock Alignment
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15 Electrical Characteristics (continued)
FRAME BOUNDARY 125 s /CT_FRAME
CT_C8
CT_DX
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
TIME SLOT
0
127
Note: Bit 1 is the MSB and Bit 8 is the LSB. MSB is always transmitted first in all transfers.
5-6120F
Figure 60. Frame Timing Diagram
Vt+ CT_C8_A CT_C8_A
Vt+
tSKC8
tSKCOMP
Vt+ CT_C8_B COMPATIBILITY CLOCKS
Vt+
Vt- tSKCOMP
5-6122F
Figure 61. Detailed Clock Skew Timing Diagram
15.6 ac Electrical Characteristics
15.6.1 Skew Timing, H-Bus Table 127. Skew Timing, H-Bus Symbol tSKC8 -- Parameter Maximum Skew Between CT_C8_A and CT_C8_B* Maximum Skew Between CT_C8_A and L_SCx Clock* Min -- -- -- Typical -- -- -- Max 10, 5 2 Unit ns ns ns
TSKCOMP Maximum Skew Between CT_C8_A and any Compatibility Clock*
* Test load--50 pF. Assumes A and B masters in adjacent slots. When static skew is 10 ns and in the same clock cycle, each clock performs a 10 ns phase correction in opposite directions, a maximum skew of 30 ns will occur during that clock cycle. Meeting the skew requirements in Table 127 and the requirements of Section 15.5 H-Bus Timing on page 169 could require the PLLs generating CT_C8 to have different time constants when acting as primary and secondary clock masters.
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15 Electrical Characteristics (continued)
Table 128. L_SC[3:0] and Frame Group Rise and Fall Time Parameter L_SCx Rise Time L_SCx Fall Time Frame Group Rise Time Frame Group Fall Time
* Worst-case loading of 50 pF on all outputs.
Min -- -- -- --
Typ -- -- -- --
Max 5 4 3 3
Unit* ns ns ns ns
15.7 Hot-Swap
The T8110 has features which assist in H.110 hot swap applications. All H.110 bus signals are put in high impedance (3-state and/or input) during the early power phase of board insertion/removal. The ECTF H.110 specification requires that all CT data lines and CT_NETREF clocks have 0.7 V applied through 18 k resistors before plugging into and releasing from the H.110 bus. A feature on the T8110 incorporates all 34 18 k precharge resistors internally (32 for the CT data signals, 2 for NETREFs). These resistors accept 0.7 V directly through the VPRECHARGE input. The ECTF H.110 specification requires that the T8110 must be powered from early power in hot swap applications. The circuit that generates the 0.7 V precharge voltage must also be powered from early power. Refer to ECTF H.110 and PICMG CompactPCI Hot Swap specifications for hot swap requirements.
15.9 APLL VDD Filter
Separate VDDs are provided for APLL1 and APLL2 for filtering purposes. VDD filtering will provide stability in the APLL, primarily the VCOs. An R/C low pass filter should be applied to the PLL VDDs, see Figure 62. Depending on the quality of VDD and board layout characteristics, the R/C values should be selected to filter out unwanted frequencies above a targeted frequency. For example, a 25 resistor and 10 F capacitor will have a cut-off frequency of 636 Hz. Characterize the quality of your VDD and select component values accordingly. 25 is the maximum recommended resistor value. At high frequencies the ESR of a bulk cap becomes a problem (no longer effectively low passes) so a high-frequency cap of 0.1 F or so is required to compensate for some of the higher clocks and various harmonics. This needs to be placed as close to the T8110 device as possible to minimize the radiational pick-up in the remaining trace length. APLL1 and APLL2 each draw approximately 7 mA at 3.3 V. Hot swap applications can use late power to ensure the capacitance and in-rush current do not violate the PICMG Hot Swap specification.
VDD = 3.3 V
15.7.1 LPUE (Local Pull-Up Enable)
LPUE is used as an assist in CompactPCI specifically for Hot Swap; see Section 2.3.2 on page 18. During live board insertion/removal, the only devices which should be on early power are the power controller and interface parts (PCI interface attached to J1, H.110 interface attached to J4). Without the LPUE, any device connected to the T8110 would get current flow from the early power through the pull-up resistors. When late power parts power up, they already have current flowing through the I/O and these devices could possibly latch up. The current flow is eliminated by LPUE disabling the pull-up resistors. LPUE is typically controlled by the power controller. The power controller will pull LPUE low during board insertion/removal and will release LPUE high so that the pull ups are re-enabled with late power turning on. Signals that have pull-ups disabled by LPUE are GP[7:0], FG[7:0], MB_D[15:0], LD[31:0], LREF[7:0], PRI_REF_IN, NR1_DIV_IN, and NR2_DIV_IN.
R APLL1VDD C 0.1 F VSS
T8110
VDD = 3.3 V
R APLL2VDD C 0.1 F VSS
15.8 Decoupling
Decoupling the T8110 VDDs with 0.1 F capacitors is recommended. 1000 pF or 0.01 F capacitors may be used in addition to the 0.1 F capacitors to provide additional decoupling.
0995(F)
Figure 62. APLL VDD Filtering
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15 Electrical Characteristics (continued)
15.10 PC Board PBGA Considerations
The T8110 is a 272-ball plastic ball grid array package. The 16 centrally located thermal balls should be connected to board ground. While there are no special printed-circuit board requirements for the T8110, there are specification requirements for PC board layout that must be adhered to. For instance, per the ECTF H.110 specification, all CT bus data signals must not exceed 4 inches in length from connector to I/O cell and all CT bus clock signals must not exceed 2 inches in length from connector to I/O cell. We advise the customer to become familiar with applicable specifications for any PC board requirements.
15.11 Unused Pins
If the PCI interface is not used, these signals should be pulled up/down to their inactive state. Multiple pins may share a common resistor. Signals with pull-up/down resistors may be left unconnected if unused. Unused 8 mA 3-state signals may be left unconnected. If XTAL1_IN and/or XTAL2_IN are being driven from an oscillator, then XTAL1_OUT and/or XTAL2_OUT must be left unconnected. If XTAL2 is not used, XTAL2_IN should be pulled-up or tied directly to VDD and XTAL2_OUT should be left unconnected. If VPRECHARGE is unused, this signal may be left unconnected. All signals listed as no connect (A20, D16, D20, E17, F20, and G17) in Table 9 must be left unconnected.
15.12 T8110 Evaluation Boards
Two development kits are available for the T8110, one for PCI and one for CompactPCI. Each kit contains an evaluation board, software, documentation and unrestricted access to the T8110 help desk. The CompactPCI evaluation board is Full Hot Swap; it includes the T8110 chip, a PCI transparent bridge, a dual T1/E1 line interface, dual codec, and dual SLIC. The PCI evaluation board is a full-length PCI board and is comparably featured (no hot swap). The CompactPCI evaluation board is designed to use the PCI interface only, and the PCI board has an option to use the PCI interface or the microprocessor interface. Software includes full source code, including rights to re-use. Documentation CD includes evaluation board schematics (ORCAD and .pdf formats) evaluation board bill of material (BOM), data sheets, and advisories. Refer to website www.agere.com/ambassador for additional information.
15.13 T8110 Ordering Information
Table 129. T8110 Ordering Information Device Part Number T-8110---BAL-DB Package 272-Ball PBGA Comcode 108560269
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16 Package Outline
16.1 Pin and Pad Assignments
LOCAL REFERENCE INPUTS
H-BUS DATA
H.110 CLOCKS
EXTERNAL CLADs/DJATs
A PRECHARGE B C D E GPIO (EEPROM) F G MINIBRIDGE ADDRESS H J K L M MINIBRIDGE CONTROL SIGNALS N P R T MINIBRIDGE DATA U V W Y RESET
VSS
PLL (XTAL#1)
VSS
VDD
VSS
VDD
VSS
VDD
VSS
PLL (XTAL#2) BIST
VDD
H.110 PE
H.100 PE
COMPATIBILITY CLOCKS
PLL MLAC JTAG PORT
VDD
VSS
VSS LOCAL CLOCK OUTPUTS
VDD
LOCAL PE VDD
VSS VIO/P_SELECT = 3.3 V or 5 V VDD (CBEs) THERMAL GROUND
VSS LOCAL DATA VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
FRAME GROUP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
ERROR SIGNALS
(PCI CONTROLS)
PCI INTERFACE 5-8906F(a).
Figure 63. T8110 Pins by Functional Group, PCI I/F Enabled, Microprocessor I/F Disabled
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16 Package Outline (continued)
LOCAL REFERENCE INPUTS
H-BUS DATA
H.110 CLOCKS
EXTERNAL CLADs/DJATs
A PRECHARGE B C D E GPIO F G PROCESSOR ADDRESS H J K L M PROCESSOR CONTROL SIGNALS N P R T PROCESSOR DATA U V W Y RESET
VSS
PLL (XTAL#1)
VSS
VDD
VSS
VDD
VSS
VDD
VSS
PLL (XTAL#2) BIST
VDD
H.110 PE
H.100 PE
COMPATIBILITY CLOCKS
PLL MLAC JTAG PORT
VDD
VSS
(N/C)
VSS LOCAL CLOCK OUTPUTS
VDD
LOCAL PE VDD
VSS VIO/P_SELECT = 0V VDD THERMAL GROUND
VSS LOCAL DATA VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
FRAME GROUP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
ERROR SIGNALS
(NO CONNECT) 5-8906F(b).
Figure 64. T8110 Pins by Functional Group, Microprocessor I/F Enabled, PCI I/F Disabled
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16
Package Outline (continued)
19 SPACES @ 1.27 = 24.13
19 20 17 15 13 11 18 16 14 12 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y
A1 BALL PAD CORNER
0.76
+0.14 -0.16
19 SPACES @ 1.27 = 24.13
5-4406
BOTTOM VIEW
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Package Outline (continued)
0.36
+0.04 -0.06
1.17 0.05
2.13
+0.19 -0.21
SEATING PLANE 0.20 0.60 0.10 SOLDER BALL
5-4406
SIDE VIEW
27.00 A1 BALL PAD CORNER +0.70 24.00 -0.50
+0.70 24.00 -0.50 27.00
5-4406
TOP VIEW
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17 JTAG/Boundary Scan
17.1 The Principle of Boundary-Scan Architecture
Each primary input signal and primary output signal is supplemented with a multipurpose memory element called a boundary-scan cell. Cells on device primary inputs are referred to as input cells and cells on primary outputs are referred to as output cells. Input and output is relative to the core logic of the device. At any time, only one register can be connected from TDI to TDO. For example, instruction register (IR), bypass, boundary-scan, ident, or even some appropriate register internal to the core logic (see Figure 65). The selected register is identified by the decoded output of the instruction register. Certain instructions are mandatory, such as EXTEST (boundary-scan register selected), whereas others are optional, such as the IDCODE instruction (Ident register selected).
INTERNAL CORE LOGIC
TDI TEST DATA IN BYPASS IDENTIFICATION REGISTER INSTRUCTION REGISTER (IR)
TDO TEST DATA OUT
TEST MODE SELECT TEST CLOCK
TMS TCK
TAP CONTROLLER
TEST RESET (TRSTN)
Figure 65. IEEE* 1149.1 Boundary-Scan Architecture
Figure 65 shows the following elements:
n A set of four dedicated test pins, test data in (TDI), test mode select (TMS), test clock (TCK), test data out
(TDO), and one optional test pin test reset (TRSTN). These pins are collectively referred to as the test access port (TAP).
n A boundary-scan cell on each device's primary input and primary output pin, connected internally to form a serial
boundary-scan register (boundary scan).
n A finite-state machine TAP controller with inputs TCK and TMS. n An n-bit (n = 3) instruction register (IR), holding the current instruction. n A 1-bit bypass register (BYPASS). n An optional 32-bit identification register (ident) capable of being loaded with a permanent device identification
code.
* IEEE is a registered trademark of The Institute of Electrical and Electronic Engineers, Inc.
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17
JTAG/Boundary Scan
17.1.1 Instruction Register The instruction register is 3 bits long and the capture value is 001. Table 130. Instruction Register Instruction EXTEST SAMPLE IDCODE BYPASS HIGH Z Binary Code 000 001 101 110, 111 010 Description Places the boundary-scan register in EXTEST mode. Places the boundary-scan register in sample mode. Identification code. Places the bypass register in the scan chain. Places all outputs and I/Os in 3-state mode.
17.2 Boundary-Scan Register
Note: The control column of the following table indicates the value for boundary-scan control of this pin. Table 131. Boundary-Scan Register Description
Boundary-Scan Register Bit Pin Pin Name VSS BOUT_CT_D_EN(27) CT_D27 BOUT_CT_D_EN(24) CT_D24 BOUT_CT_D_EN(21) CT_D21 BOUT_CT_D_EN(19) CT_D19 BOUT_CT_D_EN(16) CT_D16 BOUT_CT_D_EN(13) CT_D13 BOUT_CT_D_EN(11) CT_D11 BOUT_CT_D_EN(8) CT_D8 BOUT_CT_D_EN(4) CT_D4 BOUT_CT_D_EN(0) CT_D0 BOUT_CT_A_EN Ball A1 -- A2 -- A3 -- A4 -- A5 -- A6 -- A7 -- A8 -- A9 -- A10 -- A11 -- Enabled State Linkage Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller Pin Grouping -- -- BOUT_CT_D_EN(27) -- BOUT_CT_D_EN(24) -- BOUT_CT_D_EN(21) -- BOUT_CT_D_EN(19) -- BOUT_CT_D_EN(16) -- BOUT_CT_D_EN(13) -- BOUT_CT_D_EN(11) -- BOUT_CT_D_EN(8) -- BOUT_CT_D_EN(4) -- BOUT_CT_D_EN(0) -- Control -- -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- Disabled State -- -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z --
;
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
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17 JTAG/Boundary Scan (continued)
Table 131. Boundary-Scan Register Description (continued)
Boundary-Scan Register Bit Pin Pin Name /CT_FRAME_A CT_C8_A BOUT_CT_NETREF1_En CT_NETREF1 L_REF0 L_REF4 GENERAL_EN PRI_REF_OUT PRI_REF_IN NR1_DIV_IN PEN BOUT_CT_D_EN(29) CT_D29 BOUT_CT_D_EN(28) CT_D28 BOUT_CT_D_EN(25) CT_D25 BOUT_CT_D_EN(22) CT_D22 BOUT_CT_D_EN(20) CT_D20 BOUT_CT_D_EN(17) CT_D17 BOUT_CT_D_EN(14) CT_D14 BOUT_CT_D_EN(9) CT_D9 BOUT_CT_D_EN(6) CT_D6 BOUT_CT_D_EN(5) CT_D5 BOUT_CT_D_EN(1) CT_D1 BOUT_CT_B_EN /CT_FRAME_B CT_C8_B Ball A12 A13 -- A14 A15 A16 -- A17 A18 A19 A20 -- B1 -- B2 -- B3 -- B4 -- B5 -- B6 -- B7 -- B8 -- B9 -- B10 -- B11 -- B12 B13 Enabled State I/O I/O Controller I/O Input Input Controller Output3 Clock Input Enable0 Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O I/O Pin Grouping BOUT_CT_A_EN BOUT_CT_A_EN -- BOUT_CT_NETREF1_En BOUT_CT_NETREF1_En BOUT_CT_NETREF1_En -- GENERAL_EN GENERAL_EN GENERAL_EN GENERAL_EN(0) -- BOUT_CT_D_EN(29) -- BOUT_CT_D_EN(28) -- BOUT_CT_D_EN(25) -- BOUT_CT_D_EN(22) -- BOUT_CT_D_EN(20) -- BOUT_CT_D_EN(17) -- BOUT_CT_D_EN(14) -- BOUT_CT_D_EN(9) -- BOUT_CT_D_EN(6) -- BOUT_CT_D_EN(5) -- BOUT_CT_D_EN(1) -- BOUT_CT_B_EN BOUT_CT_B_EN Control 0 0 -- 0 -- -- -- 0 -- -- -- -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 0 Disabled State High Z High Z -- High Z -- -- -- High Z -- -- 50 K up --
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
High Z
--
High Z
--
High Z
--
High Z
--
High Z
--
High Z
--
High Z
--
High Z
--
High Z
--
High Z
--
High Z
--
High Z High Z
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17 JTAG/Boundary Scan (continued)
Table 131. Boundary-Scan Register Description (continued)
Boundary-Scan Register Bit Pin Pin Name BOUT_CT_NETREF2_En CT_NETREF2 L_REF1 L_REF5 L_REF6 NR1_SEL_OUT APLL1VDD XTAL1_IN VPRECHARGE BOUT_CT_D_EN(30) CT_D30 BOUT_CT_D_EN(26) CT_D26 BOUT_CT_D_EN(23) CT_D23 BOUT_CT_D_EN(18) CT_D18 BOUT_CT_D_EN(15) CT_D15 BOUT_CT_D_EN(12) CT_D12 BOUT_CT_D_EN(10) CT_D10 BOUT_CT_D_EN(7) CT_D7 BOUT_CT_D_EN(2) CT_D3 BOUT_CT_D_EN(3) CT_D2 BOUT_FRN_COMP_EN /FRN_COMP BOUT_SCBUS_CLOCKS_En /SCLKX2 SCLK L_REF2 L_REF3 Ball -- B14 B15 B16 B17 B18 B19 B20 C1 -- C2 -- C3 -- C4 -- C5 -- C6 -- C7 -- C8 -- C9 -- C10 -- C11 -- C12 -- C13 C14 C15 C16 Enabled State Controller I/O Input Input Input Output3 Linkage Linkage Linkage Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O I/O Input Input Pin Grouping -- BOUT_CT_NETREF2_En BOUT_CT_NETREF2_En BOUT_CT_NETREF2_En BOUT_CT_NETREF2_En GENERAL_EN -- -- -- -- BOUT_CT_D_EN(30) -- BOUT_CT_D_EN(26) -- BOUT_CT_D_EN(23) -- BOUT_CT_D_EN(18) -- BOUT_CT_D_EN(15) -- BOUT_CT_D_EN(12) -- BOUT_CT_D_EN(10) -- BOUT_CT_D_EN(7) -- BOUT_CT_D_EN(2) -- BOUT_CT_D_EN(3) -- BOUT_FRN_COMP_EN -- BOUT_SCBUS_CLOCKS_En BOUT_SCBUS_CLOCKS_En BOUT_SCBUS_CLOCKS_En BOUT_SCBUS_CLOCKS_En -- 0 -- 0 -- 0 0 -- -- Control -- 0 -- -- -- 0 -- -- -- -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- Disabled State -- High Z -- -- -- High Z -- -- -- -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- 50 k up -- 50 k up 50 k up -- --
58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93
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17 JTAG/Boundary Scan (continued)
Table 131. Boundary-Scan Register Description (continued)
Boundary-Scan Register Bit Pin Pin Name L_REF7 TRST# XTAL1_OUT NR2_DIV_IN BOUT_GP_EN(0) GP0 BOUT_CT_D_EN(31) CT_D31 BOUT_GP_EN(4) GP4 VSS H110_ENABLE VDD H100_ENABLE VSS BOUT_HMVIP_CLOCKS_En /C16+ /C16- VDD BOUT_MVIP_CLOCKS_En /C4 VSS C2 VDD PLOCK VSS TMS NR2_SEL_OUT PSEL BOUT_GP_EN(1) GP1 BOUT_GP_EN(2) GP2 BOUT_GP_EN(6) Ball C17 C18 C19 C20 -- D1 -- D2 -- D3 D4 D5 D6 D7 D8 -- D9 D10 D11 -- D12 D13 D14 D15 D16 D17 D18 D19 D20 -- E1 -- E2 -- Enabled State Input TRST Linkage Input Controller I/O Controller I/O Controller I/O Linkage Enable1 Linkage Enable0 Linkage Controller I/O I/O Linkage Controller I/O Linkage I/O Linkage Linkage Linkage TMS Output3 Linkage Controller I/O Controller I/O Controller Pin Grouping BOUT_SCBUS_CLOCKS_En BOUT_SCBUS_CLOCKS_En BOUT_SCBUS_CLOCKS_En BOUT_SCBUS_CLOCKS_En -- BOUT_GP_EN(0) -- BOUT_CT_D_EN(31) -- BOUT_GP_EN(4) -- BOUT_GP_EN(4) -- BOUT_GP_EN(4) -- BOUT_GP_EN(4) BOUT_HMVIP_CLOCKS_En BOUT_HMVIP_CLOCKS_En -- -- BOUT_MVIP_CLOCKS_En -- BOUT_MVIP_CLOCKS_En -- BOUT_MVIP_CLOCKS_En -- BOUT_MVIP_CLOCKS_En GENERAL_EN GENERAL_EN -- BOUT_GP_EN(1) -- BOUT_GP_EN(2) -- Control -- -- -- -- -- 0 -- 0 -- 0 -- -- -- -- -- -- 0 0 -- -- 0 -- 0 -- -- -- -- 0 -- -- 0 -- 0 -- Disabled State -- 50 k up -- -- -- High Z -- High Z -- High Z -- 20 k down -- 20 k down -- -- 50 k up 50 k up -- -- 50 k up -- 50 k up -- -- -- 50 k up High Z 20 k down -- High Z -- High Z --
94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
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17 JTAG/Boundary Scan (continued)
Table 131. Boundary-Scan Register Description (continued)
Boundary-Scan Register Bit Pin Pin Name GP5 BOUT_GP_EN(7) GP7 PTEST TCK APLL2VDD XTAL2_IN BOUT_MB_EN MB_A0 BOUT_GP_EN(3) GP3 BOUT_GP_EN(5) GP6 VDD VDD TDI XTAL2_OUT TESTMODE BOUT_MB_A1_EN MB_A1 BOUT_MB_A2_EN MB_A2 MB_A3 OUT_EE_CS_EN EE_CS PPDN TDO OUT_L_SC_En(3) L_SC3 OUT_TCLK_OUT_En TCLK_OUT Ball E3 -- E4 E17 E18 E19 E20 -- F1 -- F2 -- F3 F4 F17 F18 F19 F20 -- G1 -- G2 G3 -- G4 G17 G18 -- G19 -- G20 Enabled State I/O Controller I/O Linkage TCK Linkage Linkage Controller I/O Controller I/O Controller I/O Linkage Linkage TDI Linkage Enable0 Controller I/O Controller I/O I/O Controller Output3 Linkage TDO Controller Output3 Controller Output3 BOUT_GP_EN(7) -- BOUT_MB_EN -- BOUT_GP_EN(3) -- BOUT_GP_EN(5) -- -- BOUT_GP_EN(5) BOUT_GP_EN(5) BOUT_GP_EN(5) -- BOUT_MB_A1_EN -- BOUT_MB_A2_EN BOUT_MB_A2_EN -- OUT_EE_CS_EN OUT_EE_CS_EN OUT_EE_CS_EN -- OUT_L_SC_En(3) -- OUT_TCLK_OUT_En Pin Grouping BOUT_GP_EN(6) -- BOUT_GP_EN(7) BOUT_GP_EN(7) BOUT_GP_EN(7) Control 0 -- 0 -- -- -- -- -- 0 -- 0 -- 0 -- -- -- -- -- -- 0 -- 0 0 -- 0 -- -- -- 0 -- 0 Disabled State High Z -- High Z 20 k down 50 k up -- -- -- 20 k down -- High Z -- High Z -- -- 50 k up -- 20 k down -- 20 k down -- 20 k down 20 k down -- High Z 20 k down -- -- High Z -- High Z
128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158
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17 JTAG/Boundary Scan (continued)
Table 131. Boundary-Scan Register Description (continued)
Boundary-Scan Register Bit Pin Pin Name MB_A4 MB_A5 MB_A6 VSS VSS OUT_L_SC_En(2) L_SC2 OUT_L_SC_En(1) L_SC1 OUT_L_SC_En(0) L_SC0 MB_A8 MB_A9 MB_A10 MB_A7 LPUE BOUT_L_D_EN(2) L_D2 BOUT_L_D_EN(1) L_D1 BOUT_L_D_EN(0) L_D0 MB_A12 MB_A13 MB_A11 VDD BOUT_L_D_EN(3) L_D3 BOUT_L_D_EN(6) Ball H1 H2 H3 H4 H17 -- H18 -- H19 -- H20 J1 J2 J3 J4 J17 -- J18 -- J19 -- J20 K1 K2 K3 K4 -- K17 -- Enabled State I/O I/O I/O Linkage Linkage Controller Output3 Controller Output3 Controller Output3 I/O I/O I/O I/O Enable1 Controller I/O Controller I/O Controller I/O I/O I/O I/O Linkage Controller I/O Controller Pin Grouping BOUT_MB_EN BOUT_MB_EN BOUT_MB_EN -- -- -- OUT_L_SC_En(2) -- OUT_L_SC_En(1) -- OUT_L_SC_En(0) BOUT_MB_EN BOUT_MB_EN BOUT_MB_EN BOUT_MB_EN BOUT_MB_EN -- BOUT_L_D_EN(2) -- BOUT_L_D_EN(1) -- BOUT_L_D_EN(0) BOUT_MB_EN BOUT_MB_EN BOUT_MB_EN -- -- BOUT_L_D_EN(3) -- Control 0 0 0 -- -- -- 0 -- 0 -- 0 0 0 0 0 -- -- 0 -- 0 -- 0 0 0 0 -- -- 0 -- Disabled State 20 k down 20 k down 20 k down -- -- -- High Z -- High Z -- High Z 20 k down 20 k down 20 k down 20 k down 50 k up -- High Z -- High Z -- High Z 20 k down 20 k down 20 k down -- -- High Z --
159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187
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17 JTAG/Boundary Scan (continued)
Table 131. Boundary-Scan Register Description (continued)
Boundary-Scan Register Bit Pin Pin Name L_D6 BOUT_L_D_EN(5) L_D5 BOUT_L_D_EN(4) L_D4 MB_CS0 MB_CS1 MB_A14 MB_A15 VDD BOUT_L_D_EN(7) L_D7 BOUT_L_D_EN(9) L_D9 BOUT_L_D_EN(8) L_D8 MB_CS2 MB_CS3 MB_CS4 MB_CS5 BOUT_L_D_EN(11) L_D11 BOUT_L_D_EN(10) L_D10 BOUT_L_D_EN(13) L_D13 BOUT_L_D_EN(12) L_D12 MB_RD OUT_MB_CS6_EN MB_CS6 MB_CS7 Ball K18 -- K19 -- K20 L1 L2 L3 L4 L17 -- L18 -- L19 -- L20 M1 M2 M3 M4 -- M17 -- M18 -- M19 -- M20 N1 -- N2 N3 Enabled State I/O Controller I/O Controller I/O I/O I/O I/O I/O Linkage Controller I/O Controller I/O Controller I/O I/O I/O I/O I/O Controller I/O Controller I/O Controller I/O Controller I/O I/O Controller Output3 I/O Pin Grouping BOUT_L_D_EN(6) -- BOUT_L_D_EN(5) -- BOUT_L_D_EN(4) BOUT_MB_EN BOUT_MB_EN BOUT_MB_EN BOUT_MB_EN -- -- BOUT_L_D_EN(7) -- BOUT_L_D_EN(9) -- BOUT_L_D_EN(8) BOUT_MB_EN BOUT_MB_EN BOUT_MB_EN BOUT_MB_EN -- BOUT_L_D_EN(11) -- BOUT_L_D_EN(10) -- BOUT_L_D_EN(13) -- BOUT_L_D_EN(12) BOUT_MB_EN -- OUT_MB_CS6_EN BOUT_MB_EN Control 0 -- 0 -- 0 0 0 0 0 -- -- 0 -- 0 -- 0 0 0 0 0 -- 0 -- 0 -- 0 -- 0 0 -- 0 0 Disabled State High Z -- High Z -- High Z 20 k down 20 k down 20 k down 20 k down -- -- High Z -- High Z -- High Z 20 k down 20 k down High Z High Z -- High Z -- High Z -- High Z -- High Z High Z -- High Z High Z
188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219
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17 JTAG/Boundary Scan (continued)
Table 131. Boundary-Scan Register Description (continued)
Boundary-Scan Register Bit Pin Pin Name VSS VSS BOUT_L_D_EN(15) L_D15 BOUT_L_D_EN(14) L_D14 BOUT_L_D_EN(16) L_D16 MB_WR BOUT_MB_D_En MB_D14 MB_D15 MB_D11 BOUT_L_D_EN(23) L_D23 BOUT_L_D_EN(19) L_D19 BOUT_L_D_EN(18) L_D18 BOUT_L_D_EN(17) L_D17 MB_D12 MB_D13 MB_D10 VDD VDD BOUT_L_D_EN(22) L_D22 BOUT_L_D_EN(21) L_D21 bout_L_D_EN(20) L_D20 MB_D8 MB_D9 MB_D6 MB_D7 Ball N4 N17 -- N18 -- N19 -- N20 P1 -- P2 P3 P4 -- P17 -- P18 -- P19 -- P20 R1 R2 R3 R4 R17 -- R18 -- R19 -- R20 T1 T2 T3 T4 Enabled State Linkage Linkage Controller I/O Controller I/O Controller I/O I/O Controller I/O I/O I/O Controller I/O Controller I/O Controller I/O Controller I/O I/O I/O I/O Linkage Linkage Controller I/O Controller I/O Controller I/O I/O I/O I/O I/O Pin Grouping -- -- -- BOUT_L_D_EN(15) -- BOUT_L_D_EN(14) -- BOUT_L_D_EN(16) BOUT_MB_EN -- BOUT_MB_D_En BOUT_MB_D_En BOUT_MB_D_En -- BOUT_L_D_EN(23) -- BOUT_L_D_EN(19) -- BOUT_L_D_EN(18) -- BOUT_L_D_EN(17) BOUT_MB_D_En BOUT_MB_D_En BOUT_MB_D_En -- -- -- BOUT_L_D_EN(22) -- BOUT_L_D_EN(21) -- BOUT_L_D_EN(20) BOUT_MB_D_En BOUT_MB_D_En BOUT_MB_D_En BOUT_MB_D_En Control -- -- -- 0 -- 0 -- 0 0 -- 0 0 0 -- 0 -- 0 -- 0 -- 0 0 0 0 -- -- -- 0 -- 0 -- 0 0 0 0 0 Disabled State -- -- -- High Z -- High Z -- High Z High Z -- High Z High Z High Z -- High Z -- High Z -- High Z -- High Z High Z High Z High Z -- -- -- High Z -- High Z -- High Z High Z High Z High Z High Z
220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
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17 JTAG/Boundary Scan (continued)
Table 131. Boundary-Scan Register Description (continued)
Boundary-Scan Register Bit Pin Pin Name BOUT_L_D_EN(31) L_D31 BOUT_L_D_EN(26) L_D26 BOUT_L_D_EN(25) L_D25 BOUT_L_D_EN(24) L_D24 MB_D4 MB_D5 MB_D3 VSS VIO/P_SELECT VDD INV_PCI_CBE3_EN_N PCI_CBE3# VSS INV_PCI_CBE2_EN_N PCI_CBE2# VDD INV_PCI_PAR_EN_N PCI_PAR INV_PCI_CBE1_EN_N PCI_CBE1# VSS INV_PCI_CBE0_EN_N PCI_CBE0# VDD INV_PCI_ADEN_N(3) PCI_AD3 VSS BOUT_L_D_EN(30) L_D30 BOUT_L_D_EN(29) L_D29 BOUT_L_D_EN(27) Ball -- T17 -- T18 -- T19 -- T20 U1 U2 U3 U4 U5 U6 -- U7 U8 -- U9 U10 -- U11 -- U12 U13 -- U14 U15 -- U16 U17 -- U18 -- U19 -- Enabled State Controller I/O Controller I/O Controller I/O Controller I/O I/O I/O I/O Linkage Input Linkage Controller I/O Linkage Controller I/O Linkage Controller I/O Controller I/O Linkage Controller I/O Linkage Controller I/O Linkage Controller I/O Controller I/O Controller Pin Grouping -- BOUT_L_D_EN(31) -- BOUT_L_D_EN(26) -- BOUT_L_D_EN(25) -- BOUT_L_D_EN(24) BOUT_MB_D_En BOUT_MB_D_En BOUT_MB_D_En -- -- -- -- INV_PCI_CBE3_EN_N -- -- INV_PCI_CBE2_EN_N -- -- INV_PCI_PAR_EN_N -- INV_PCI_CBE1_EN_N -- -- INV_PCI_CBE0_EN_N -- -- INV_PCI_ADEN_N(3) -- -- BOUT_L_D_EN(30) -- BOUT_L_D_EN(29) -- Control -- 0 -- 0 -- 0 -- 0 0 0 0 -- -- -- -- 0 -- -- 0 -- -- 0 -- 0 -- -- 0 -- -- 0 -- -- 0 -- 0 -- Disabled State -- High Z -- High Z -- High Z -- High Z High Z High Z High Z -- -- -- -- High Z -- -- High Z -- -- High Z -- High Z -- -- High Z -- -- High Z -- -- High Z -- High Z --
256 257 258 259 260 261 262 263 264 265 266 267 268 269 270
271 272 273 274 275
276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291
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17 JTAG/Boundary Scan (continued)
Table 131. Boundary-Scan Register Description (continued)
Boundary-Scan Register Bit Pin Pin Name L_D27 MB_D1 MB_D2 SYSERR INV_PCI_ADEN_N(31) PCI_AD31 INV_PCI_ADEN_N(30) PCI_AD30 INV_PCI_ADEN_N(27) PCI_AD27 INV_PCI_ADEN_N(23) PCI_AD23 INV_PCI_ADEN_N(19) PCI_AD(19) INV_PCI_ADEN_N(18) PCI_AD18 PCI_LOCK# INV_PCI_CTRL_EN_N PCI_STOP# INV_PCI_SERR_OUT_N PCI_SERR# INV_PCI_ADEN_N(15) PCI_AD15 INV_PCI_ADEN_N(11) PCI_AD11 INV_PCI_ADEN_N(7) PC_AD7 INV_PCI_ADEN_N(2) PCI_AD2 BOUT_FG_EN(7) FG7 BOUT_FG_EN(6) FG6 BOUT_FG_EN(5) FG5 BOUT_L_D_EN(28) L_D28 Ball U20 V1 V2 V3 -- V4 -- V5 -- V6 -- V7 -- V8 -- V9 V10 -- V11 -- V12 -- V13 -- V14 -- V15 -- V16 -- V17 -- V18 -- V19 -- V20 Enabled State I/O I/O I/O Output3 Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Input Controller I/O Controller Output3 Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Pin Grouping BOUT_L_D_EN(27) BOUT_MB_D_En BOUT_MB_D_En GENERAL_EN -- INV_PCI_ADEN_N(31) -- INV_PCI_ADEN_N(30) -- INV_PCI_ADEN_N(27) -- INV_PCI_ADEN_N(23) -- INV_PCI_ADEN_N(19) -- INV_PCI_ADEN_N(18) INV_PCI_ADEN_N(18) -- INV_PCI_CTRL_EN_N -- INV_PCI_SERR_OUT_N -- INV_PCI_ADEN_N(15) -- INV_PCI_ADEN_N(11) -- INV_PCI_ADEN_N(7) -- INV_PCI_ADEN_N(2) -- BOUT_FG_EN(7) -- BOUT_FG_EN(6) -- BOUT_FG_EN(5) -- BOUT_L_D_EN(28) -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z Control 0 0 0 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 Disabled State High Z High Z High Z High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z
292 293 294 295 296 297 298 299 300 301
302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328
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17 JTAG/Boundary Scan (continued)
Table 131. Boundary-Scan Register Description (continued)
Boundary-Scan Register Bit Pin 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 357 359 360 361 362 363 364 365 366 Pin Name MB_D0 CLKERR INV_PCI_REQ_EN_N PCI_REQ# PCI_GNT# INV_PCI_ADEN_N(29) PCI_AD29 INV_PCI_ADEN_N(26) PCI_AD26 INV_PCI_ADEN_N(22) PCI_AD22 INV_PCI_ADEN_N(21) PCI_AD21 INV_PCI_ADEN_N(17) PCI_AD17 PCI_IDSEL# PCI_DEVSEL# INV_PCI_PERR_EN_N PCI_PERR# INV_PCI_ADEN_N(14) PCI_AD14 INV_PCI_ADEN_N(10) PCI_AD10 INV_PCI_ADEN_N(9) PCI_AD9 INV_PCI_ADEN_N(6) PCI_AD6 INV_PCI_ADEN_N(1) PCI_AD1 BOUT_FG_EN(4) FG4 BOUT_FG_EN(3) FG3 BOUT_FG_EN(2) FG2 RESET# PCI_RST# PCI_CLK Ball W1 W2 -- W3 W4 -- W5 -- W6 -- W7 -- W8 -- W9 W10 W11 -- W12 -- W13 -- W14 -- W15 -- W16 -- W17 -- W18 -- W19 -- W20 Y1 Y2 Y3 Enabled State I/O Output3 Controller Output3 Input Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Input I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Input Input Clock Pin Grouping BOUT_MB_D_En GENERAL_EN -- INV_PCI_REQ_EN_N INV_PCI_REQ_EN_N INV_PCI_REQ_EN_N INV_PCI_ADEN_N(29) -- INV_PCI_ADEN_N(26) -- INV_PCI_ADEN_N(22) -- INV_PCI_ADEN_N(21) -- INV_PCI_ADEN_N(17) -- INV_PCI_CTRL_EN_N -- INV_PCI_PERR_EN_N -- INV_PCI_ADEN_N(14) -- INV_PCI_ADEN_N(10) -- INV_PCI_ADEN_N(9) -- INV_PCI_ADEN_N(6) -- INV_PCI_ADEN_N(1) -- BOUT_FG_EN(4) -- BOUT_FG_EN(3) -- BOUT_FG_EN(2) BOUT_FG_EN(2) BOUT_FG_EN(2) BOUT_FG_EN(2) Control 0 0 -- 0 -- -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- -- -- Disabled State High Z High Z -- High Z -- -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z 50 k up -- --
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17 JTAG/Boundary Scan (continued)
Table 131. Boundary-Scan Register Description (continued)
Boundary-Scan Register Bit Pin 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 Pin Name INV_OUT_PCI_INTAN PCI_INTA# INV_PCI_ADEN_N(28) PCI_AD28 INV_PCI_ADEN_N(25) PCI_AD25 INV_PCI_ADEN_N(24) PCI_AD24 INV_PCI_ADEN_N(20) PCI_AD20 INV_PCI_ADEN_N(16) PCI_AD16 INV_PCI_FRAME_EN_N PCI_FRAME# INV_PCI_IRDY_EN_N PCI_IRDY# PCI_TRDY# INV_PCI_ADEN_N(13) PCI_AD13 INV_PCI_ADEN_N(12) PCI_AD12 INV_PCI_ADEN_N(8) PCI_AD8 INV_PCI_ADEN_N(5) PCI_AD5 INV_PCI_ADEN_N(4) PCI_AD4 INV_PCI_ADEN_N(0) PC_AD0 BOUT_FG_EN(1) FG1 BOUT_FG_EN(0) FG0 Ball -- Y4 -- Y5 -- Y6 -- Y7 -- Y8 -- Y9 -- Y10 -- Y11 Y12 -- Y13 -- Y14 -- Y15 -- Y16 -- Y17 -- Y18 -- Y19 -- Y20 Enabled State Controller Output3 Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Controller I/O Pin Grouping -- INV_OUT_PCI_INTAn -- INV_PCI_ADEN_N(28) -- INV_PCI_ADEN_N(25) -- INV_PCI_ADEN_N(24) -- INV_PCI_ADEN_N(20) -- INV_PCI_ADEN_N(16) -- INV_PCI_FRAME_EN_N -- INV_PCI_IRDY_EN_N INV_PCI_CTRL_EN_N -- INV_PCI_ADEN_N(13) -- INV_PCI_ADEN_N(12) -- INV_PCI_ADEN_N(8) -- INV_PCI_ADEN_N(5) -- INV_PCI_ADEN_N(4) -- INV_PCI_ADEN_N(0) -- BOUT_FG_EN(1) -- BOUT_FG_EN(0) Control -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 Disabled State -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z -- High Z
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Appendix A. Constant and Minimum Delay Connections
A.1 Connection Definitions
A forward connection is defined as one in which the output to time slot has a greater value than the input from time-slot, or, put another way, the delta between them is positive. A reverse connection is defined as one in which the output to time slot has a lesser value than the input from time slot, and the delta between them is negative. For example, going from TS(1) to TS(38) is a forward connection, and the TS is +37, but going from TS(38) to TS(1) is a reverse connection, with a TS of -37: where TS = TS(to) - TS(from). Similarly, a delta can be introduced for streams which will have a bearing in certain exceptions (discussed later): STR = STR(to) - STR(from). There is only one combination which forms a TS of +127 or -127: TS = TS(127) - TS(0) = +127, and TS = TS(0) - TS(127) = -127, but there are two combinations which form TSs of +126 or -126: TS = TS(127) - TS(1) = TS(126) - TS(0) = +126, and TS = TS(1) - TS(127) = TS(0) - TS(126) = -126, there are three combinations which yield +125 or -125, and so on. The user can utilize the TS to control the latency of the resulting connection. In some cases, the latency must be minimized. In other cases, such as a block of connections which must maintain some relative integrity while crossing a frame boundary, the required latency of some of the connections may exceed a one frame (>128 time-slots) to maintain the integrity of this virtual frame. The device uses a control bit at each connection memory location, VFC, for controlling latency, allowing each connection to select one of two alternating data buffers.
A.2 Delay Type Definitions
Constant Delay--This is a well-defined, predictable, and linear region of latency in which the to time slot is at least 128 time slots after the from time-slot, but no more than 256 time slots after the from time-slot. Mathematically, constant delay latency is described as follows*, with L denoting latency, and VFC set to the value indicated: Forward connections, VFC = 1: L = 128 + TS (0 TS 127) Reverse connections, VFC = 0: L = 256 + TS (-127 TS 0) Example: Switching from TS(37) to TS(1) as a constant delay, the delta is -36, so FME is set to 0 and the resulting latency is 256 - 36 = 220 time slots. Thus, the connection will be made from TS(37) of frame(n) to TS(1) of frame(n + 2). Use constant delay for latencies of 128 to 256 time slots, set VFC = 1 for forward connections, set VFC = 0 for reverse connections.
Simple summary:
* Since TS = TS(to) -TS(from), the user can modify the equations to solve for either TS(to) or TS(from).
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Appendix A. Constant and Minimum Delay Connections (continued)
127
255
VF C =1
APPLIED DELTA (TIME SLOTS)
0
128
RESULTING LATENCY (TIME SLOTS)
=0
256
C VF
-127
129
Figure 66. Constant Delay Connection Latency
Minimum Delay--This is the most common type of switching, but has a shorter range than constant delay, and the user must be aware of exceptions caused by interactions between the device's internal pipeline and the dual buffering. The to time slot is at least 3 time slots after the from time slot, but no more than 128 time slots after the from time slot. Exceptions exist at TSs of +1, +2, -126, and -127. Forward connections, VFC = 0: L = TS (3 TS 127). Reverse connections, VFC = 1: L = 128 + TS (-125 TS 0). Example: Using the same switching from the example above, TS(37) to TS(1), the delta is -36, so VFC is set to 1 to effect the minimum delay (setting to 0 effects constant delay), and the resulting latency is 128 - 36 = 92 time slots. The relative positions of the end time slots are the same in both minimum and constant delay, i.e., they both switch to TS(1)], but the actual data is delayed by an additional frame in the constant delay case. Use minimum delay for latencies of 3 to 128 time slots, set VFC = 0 for forward connections, set VFC = 1 for reverse connections.
Simple summary:
Exceptions to minimum delay--Up until this point in the discussion, the STRs have not been discussed because the to and from streams have been irrelevant in the switching process. Note: The one universally disallowed connection on the device is a TS of 0 and a STR of 0. This is, of course, a stream + time-slot switching to itself! Rather than try to list the exceptions mathematically, a table is provided. The latencies in these cases may exceed two frames due to the interaction of the intrinsic pipeline delays with the double buffering. Agere Systems Inc. 191
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Data Sheet May 2001
Appendix A. Constant and Minimum Delay Connections (continued)
Table 132. Special Cases (Exceptions) VFC Value 0 0 1 1 TS +1 +2 -126 -127 Latency for STR < 0 257 258 258 257 Latency for STR 0 257 2 2 257
Graphically, the minimum delay latency equations are illustrated below. The exceptions to the minimum delay have been included in the diagram, connected to the main function by dashed lines.
127
127
C VF =0
2 APPLIED DELTA (TIME SLOTS)
SPECIAL LONG LATENCY CONNECTIONS (SEE TEXT)
258
2
0
0
RESULTING LATENCY (TIME SLOTS)
=1
128......256
C VF
-126 -127 2 257
5-6224
Figure 67. Minimum Delay Connection Latency
Lower Stream Rates--The discussion has centered on 128 time-slot frames which correspond to 8.192 Mbits/s data rates. How does one make similar predictions for lower stream rates? For 4.096 Mbits/s, multiply the to and from time-slot values by two, i.e., time slot 0 at 4.096 Mbits/s corresponds to time slot 0 at 8.192 Mbits/s, and time slot 63 at 4.096 Mbits/s corresponds to time slot 126 at 8.192 Mbits/s. Similarly, multiply values by four to convert 2.048 Mbits/s values. The latency equations can then be applied directly.
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Appendix B. Register Bit Field Mnemonic Summary
Key to using the table below:
n Five character alphanumeric designation n Character 4 indicates the general register type as follows:
-- Divide = load value for divider -- Enable = bit or bits to enable a function -- Load = load value, typically for counter -- Output = output only -- Select = bit or bits select multiple functions
n Character 5 indicates the size as follows:
-- B = bit -- N = nibble -- P = partial register (2, 3, 5, 6, or 7 bits) -- R = register
n Position column identifies the bit position in the register:
-- 0, 1, 2, 3, 4, 5, 6, 7 for bits -- L for lower nibble -- U for upper nibble -- n-m for bit positions in a partial register Table 133. Mnemonic Summary, Sorted by Name Mnemonic A1HLR A1LOB A1SLR A2HLR A2SLR A3HLR A3SLR A4HLR A4SLR A5HLR A5SLR A6HLR A6SLR A7HLR A7SLR ABOEN ACRSN AIOEB BA0LR BA1LR BA2LR BA3LR BCRSN C2FEB Description MB_CS1 address hold APLL1 lock indicator MB_CS1 address setup MB_CS2 address hold MB_CS2 address setup MB_CS3 address hold MB_CS3 address setup MB_CS4 address hold MB_CS4 address setup MB_CS5 address hold MB_CS5 address setup MB_CS6 address hold MB_CS6 address setup MB_CS7 address hold MB_CS7 address setup A and B clocks output A clocks rate All I/O (master) DT base address byte 0 DT base address byte 1 DT base address byte 2 DT base address byte 3 B clocks rate C2 fallback trigger Type Load Output Load Load Load Load Load Load Load Load Load Load Load Load Load Enable Select Enable Load Load Load Load Select Enable Register 0x00717 0x00125 0x00713 0x00727 0x00723 0x00737 0x00733 0x00747 0x00743 0x00757 0x00753 0x00767 0x00763 0x00777 0x00773 0x00220 0x00223 0x00103 0x00110 0x00111 0x00112 0x00113 0x00223 0x0010A Bit Position -- 7 -- -- -- -- -- -- -- -- -- -- -- -- -- U L 7 -- -- -- -- U 5
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Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 133. Mnemonic Summary, Sorted by Name (continued) Mnemonic C2LOB C2TOB C2WEB C4FEB C4LOB C4TOB C4WEB CAFEB CALOB CATOB CAWEB CAWSN CBFEB CBLOB CBTOB CBWEB CBWSN CCOEN CCSEN CFBOB CFHLN CFLLR CFPOB CFSEN CFSOB CKMDR CKMSR CKRDR CMFEB CMLOB CMROB CMTOB CMWEB CPFEB CPLOB CPTOB CPWEB CSASR D1FEB D1ISR D1LOB Description C2 latched error C2 transient error C2 watchdog /C4 fallback trigger C4 latched error C4 transient error /C4 watchdog C8A fallback trigger C8A latched error C8A transient error C8A watchdog C8A watchdog C8B fallback trigger C8B latched error C8B transient error C8B watchdog C8B watchdog C clocks output C clocks separate Fallback status Diag sync-to-frame high Diag sync-to-frame low CLEAR_FALLBACK pending Diag sync-to-frame EN Failsafe status Clock main Clock main Clock resource /C16- fallback trigger /C16- latched error Connection memory reset active /C16- transient error /C16- watchdog /C16+ fallback trigger /C16+ latched error /C16+ transient error /C16+ watchdog Clock set access DPLL1 sync trigger DPLL1 input DPLL1 sync latched error Type Output Output Enable Enable Output Output Enable Enable Output Output Enable Select Enable Output Output Enable Select Enable Enable Output Load Load Output Enable Output Divide Select Divide Enable Output Output Output Enable Enable Output Output Enable Select Enable Select Output Register 0x00122 0x00120 0x0010E 0x0010A 0x00122 0x00120 0x0010E 0x0010A 0x00122 0x00120 0x0010E 0x0010C 0x0010A 0x00122 0x00120 0x0010E 0x0010C 0x00220 0x00224 0x00127 0x0014B 0x0014A 0x00124 0x0014B 0x00127 0x00201 0x00200 0x00205 0x0010A 0x00122 0x00125 0x00120 0x0010E 0x0010A 0x00122 0x00120 0x0010E 0x00106 0x0010B 0x0020A 0x00123 Bit Position 5 5 5 4 4 4 4 0 0 0 0 L 1 1 1 1 U L L 6 L -- 1 U 7 -- -- -- 3 3 1 3 3 2 2 2 2 -- 5 -- 5
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Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 133. Mnemonic Summary, Sorted by Name (continued) Mnemonic D1LOP D1RSR D1TOB D1WEB D2FEB D2ISR D2LOB D2LOP D2RSR D2TOB D2WEB DMMSP DMPOB DMSOB DMTOB DPGOB EBOLR F0DSB F0IOB F0ISB F0LLR F0MEB F0RSR F0ULR F0WSP F1DSB F1IOB F1ISB F1LLR F1MEB F1RSR F1ULR F1WSP F2DSB F2IOB F2ISB F2LLR F2MEB F2RSR F2ULR F2WSP Description DPLL1 lock status DPLL1 rate DPLL1 sync transient error DPLL1 sync watchdog DPLL2 sync trigger DPLL2 input DPLL2 sync latched error DPLL2 lock status DPLL2 rate DPLL2 sync transient error DPLL2 sync watchdog Data memory mode Data memory PCI error status Data memory PCI queue status Data memory PCI timer status Data memory active page Diag external buffer retry FGIO 0 R/W direction FGIO 0 data Frame 0 pulse inversion Frame 0 lower start time FGIO 0 read mask Frame 0 pulse width rate Frame 0 upper start time Frame 0 pulse width FGIO 1 R/W direction FGIO 1 data Frame 1 pulse inversion Frame 1 lower start time FGIO 1 read mask Frame 1 pulse width rate Frame 1 upper start time Frame 1 pulse width FGIO 2 R/W direction FGIO 2 data Frame 2 pulse inversion Frame 2 lower start time FGIO 2 read mask Frame 2 pulse width rate Frame 2 upper start time Frame 2 pulse width Type Output Select Output Enable Enable Select Output Output Select Output Enable Select Output Output Output Output Load Select Load Enable Load Enable Select Load Select Select Load Enable Load Enable Select Load Select Select Load Enable Load Enable Select Load Select Register 0x00125 0x0020B 0x00121 0x0010F 0x0010B 0x0020E 0x00123 0x00125 0x0020F 0x00121 0x0010F 0x00105 0x00127 0x00126 0x00127 0x00125 0x00147 0x00482 0x00480 0x00402 0x00400 0x00481 0x00403 0x00401 0x00402 0x00482 0x00480 0x00412 0x00410 0x00481 0x00413 0x00411 0x00412 0x00482 0x00480 0x00422 0x00420 0x00481 0x00423 0x00421 0x00422 Bit Position 5:4 -- 5 5 6 -- 6 3:2 -- 6 6 6:0 0 0 3 0 -- 0 0 7 -- 0 -- -- 6:0 1 1 7 -- 1 -- -- 6:0 2 2 7 -- 2 -- -- 6:0
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Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 133. Mnemonic Summary, Sorted by Name (continued) Mnemonic F3DSB F3IOB F3ISB F3LLR F3MEB F3RSR F3ULR F3WSP F4DSB F4IOB F4ISB F4LLR F4MEB F4RSR F4ULR F4WSP F5DSB F5IOB F5ISB F5LLR F5MEB F5RSR F5ULR F5WSP F6DSB F6IOB F6ISB F6LLR F6MEB F6RSR F6ULR F6WSP F7DSB F7IOB F7ISB F7LLR F7MEB F7MSR F7RSR F7SSP F7ULR Description FGIO 3 R/W direction FGIO 3 data Frame 3 pulse inversion Frame 3 lower start time FGIO 3 read mask Frame 3 pulse width rate Frame 3 upper start time Frame 3 pulse width FGIO 4 R/W direction FGIO 4 data Frame 4 pulse inversion Frame 4 lower start time FGIO 4 read mask Frame 4 pulse width rate Frame 4 upper start time Frame 4 pulse width FGIO 5 R/W direction FGIO 5 data Frame 5 pulse inversion Frame 5 lower start time FGIO 5 read mask Frame 5 pulse width rate Frame 5 upper start time Frame 5 pulse width FGIO 6 R/W direction FGIO 6 data Frame 6 pulse inversion Frame 6 lower start time FGIO 6 read mask Frame 6 pulse width rate Frame 6 upper start time Frame 6 pulse width FGIO 7 R/W direction FGIO 7 data Frame 7 pulse inversion Frame 7 lower start time FGIO 7 read mask Frame 7 mode Frame 7 pulse width rate FG7 timer pulse shape Frame 7 upper start time Type Select Load Enable Load Enable Select Load Select Select Load Enable Load Enable Select Load Select Select Load Enable Load Enable Select Load Select Select Load Enable Load Enable Select Load Select Select Load Enable Load Enable Select Select Select Load Register 0x00482 0x00480 0x00432 0x00430 0x00481 0x00433 0x00431 0x00432 0x00482 0x00480 0x00442 0x00440 0x00481 0x00443 0x00441 0x00442 0x00482 0x00480 0x00452 0x00450 0x00481 0x00453 0x00451 0x00452 0x00482 0x00480 0x00462 0x00460 0x00481 0x00463 0x00461 0x00462 0x00482 0x00480 0x00472 0x00470 0x00481 0x00476 0x00473 0x00477 0x00471 Bit Position 3 3 7 -- 3 -- -- 6:0 4 4 7 -- 4 -- -- 6:0 5 5 7 -- 5 -- -- 6:0 6 6 7 -- 6 -- -- 6:0 7 7 7 -- 7 -- -- -- --
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Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 133. Mnemonic Summary, Sorted by Name (continued) Mnemonic F7WSN F7WSP FAFEB FALOB FATOB FAWEB FB1SB FB2SB FBCSR FBFEB FBFOB FBLOB FBSOP FBTOB FBWEB FCFEB FCISB FCLLR FCLOB FCTOB FCULR FCWEB FFPOB FGREB FPASR FRMSB FRSEN FRWSR FSCSR FSEER FSLOB FSMSN FSSSR FSTOB FSWEB FT0EB FT1EB FT2EB FT3EB FT4EB FT5EB Description FG7 timer pulse width Frame 7 pulse width /FRAMEA fallback trigger /FRAMEA latched error /FRAMEA transient error /FRAMEA watchdog APLL1 feedback reset APLL2 feedback reset Fallback control /FRAMEB fallback trigger Fallback enable status /FRAMEB latched error Fallback states /FRAMEB transient error /FRAMEB watchdog /FR_COMP fallback trigger FG7 timer invert output Frame group 7 lower count /FR_COMP latched error /FR_COMP transient error Frame group 7 upper count /FR_COMP watchdog FORCE_FALLBACK pending Frame group Frame phase alignment Diag /FR_COMP input /FR_COMP separate /FR_COMP width Failsafe return command Failsafe enable Failsafe latched error Fallback secondary mode Failsafe sensitivity Failsafe transient error Failsafe watchdog FG0 test-point FG1 test-point FG2 test-point FG3 test-point FG4 test-point FG5 test-point Type Select Select Enable Output Output Enable Select Select Select Enable Output Output Output Output Enable Enable Select Load Output Output Load Enable Output Enable Select Select Enable Select Select Enable Output Select Select Output Enable Enable Enable Enable Enable Enable Enable Register 0x00477 0x00472 0x0010B 0x00123 0x00121 0x0010F 0x00146 0x00146 0x00108 0x0010B 0x00124 0x00123 0x00124 0x00121 0x0010F 0x0010B 0x00477 0x00474 0x00123 0x00121 0x00475 0x0010F 0x00124 0x00103 0x00107 0x00145 0x00224 0x00222 0x00114 0x00115 0x00123 0x00109 0x00116 0x00121 0x0010F 0x00140 0x00140 0x00140 0x00140 0x00140 0x00140 Bit Position L 6:0 0 0 0 0 1 2 -- 1 7 1 6:4 1 1 2 7 -- 2 2 -- 2 0 5 -- 4 U -- -- -- 7 L -- 7 7 0 1 2 3 4 5
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Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 133. Mnemonic Summary, Sorted by Name (continued) Mnemonic FT6EB FT7EB FTPSR FTRSN G0DSB G0IOB G0MEB G0OEB G1DSB G1IOB G1MEB G1OEB G2DSB G2IOB G2MEB G2OEB G3DSB G3IOB G3MEB G4DSB G4IOB G4MEB G5DSB G5IOB G5MEB G6DSB G6IOB G6MEB G7DSB G7IOB G7MEB GOPOB GPIEB GSREB GT0EB GT1EB GT2EB GT3EB GT4EB GT5EB GT6EB Description FG6 test-point FG7 test-point FG test-point MUX Fallback type GPIO 0 R/W direction GPIO 0 data GPIO 0 read mask GPIO 0 override GPIO 1 R/W direction GPIO 1 data GPIO 1 read mask GPIO 0 override GPIO 2 R/W direction GPIO 2 data GPIO 2 read mask GPIO 2 override GPIO 3 R/W direction GPIO 3 data GPIO 3 read mask GPIO 4 R/W direction GPIO 4 data GPIO 4 read mask GPIO 5 R/W direction GPIO 5 data GPIO 5 read mask GPIO 6 R/W direction GPIO 6 data GPIO 6 read mask GPIO 7 R/W direction GPIO 7 data GPIO 7 read mask Go clocks pending General purpose I/O Global subrate GP0 test-point GP1 test-point GP2 test-point GP3 test-point GP4 test-point GP5 test-point GP6 test-point Type Enable Enable Select Select Select Load Enable Enable Select Load Enable Enable Select Load Enable Enable Select Load Enable Select Load Enable Select Load Enable Select Load Enable Select Load Enable Output Enable Enable Enable Enable Enable Enable Enable Enable Enable Register 0x00140 0x00140 0x00141 0x00109 0x00502 0x00500 0x00501 0x00503 0x00502 0x00500 0x00501 0x00503 0x00502 0x00500 0x00501 0x00503 0x00502 0x00500 0x00501 0x00502 0x00500 0x00501 0x00502 0x00500 0x00501 0x00502 0x00500 0x00501 0x00502 0x00500 0x00501 0x00124 0x00103 0x00105 0x00142 0x00142 0x00142 0x00142 0x00142 0x00142 0x00142 Bit Position 6 7 -- U 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 7 2 4 7 0 1 2 3 4 5 6
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Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 133. Mnemonic Summary, Sorted by Name (continued) Mnemonic GT7EB GTPSR HARSN HBRSN HCKEB HCRSN HDBEB HDRSN HERSN HFRSN HGRSN HHRSN HRBEB IASLR IC0SB IC1SB IC2SB IC3SB IC4SB IC5SB IC6SB IC7SB ICDSP ICKLP ICMSB IDHOR IDLOR IEXLP IF0SB IF1SB IF2SB IF3SB IF4SB IF5SB IF6SB IF7SB IG0SB IG1SB IG2SB IG3SB IG4SB Description GP7 test-point GP test-point MUX H1x0 group A rate H1x0 group B rate H1x0 clocks H1x0 group C rate H1x0 data bus H1x0 group D rate H1x0 group E rate H1x0 group F rate H1x0 group G rate H1x0 group H rate Hard reset of back end Diag, SYSERR assertion Invert MB CS0 strobe Invert MB CS1 strobe Invert MB CS2 strobe Invert MB CS3 strobe Invert MB CS4 strobe Invert MB CS5 strobe Invert MB CS6 strobe Invert MB CS7 strobe Diag, internal control mode Diag, internal control CLKERR Invert clock main Device ID high Device ID low Diag, internal control EXTERR Invert interrupt FGIO 0 Invert interrupt FGIO 1 Invert interrupt FGIO 2 Invert interrupt FGIO 3 Invert interrupt FGIO 4 Invert interrupt FGIO 5 Invert interrupt FGIO 6 Invert interrupt FGIO 7 Invert interrupt GPIO 0 Invert interrupt GPIO 1 Invert interrupt GPIO 2 Invert interrupt GPIO 3 Invert interrupt GPIO 4 Type Enable Select Select Select Enable Select Enable Select Select Select Select Select Enable Load Select Select Select Select Select Select Select Select Select Load Select Output Output Load Select Select Select Select Select Select Select Select Select Select Select Select Select Register 0x00142 0x00143 0x00300 0x00300 0x00103 0x00301 0x00103 0x00301 0x00302 0x00302 0x00303 0x00303 0x00101 0x00149 0x00780 0x00780 0x00780 0x00780 0x00780 0x00780 0x00780 0x00780 0x00148 0x00148 0x00204 0x0012B 0x0012A 0x00148 0x00603 0x00603 0x00603 0x00603 0x00603 0x00603 0x00603 0x00603 0x00607 0x00607 0x00607 0x00607 0x00607 Bit Position 7 -- L U 3 L 2 U L U L U 1 -- 0 1 2 3 4 5 6 7 7:6 5:4 4 -- -- 1:0 0 1 2 3 4 5 6 7 0 1 2 3 4
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Data Sheet May 2001
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 133. Mnemonic Summary, Sorted by Name (continued) Mnemonic IG5SB IG6SB IG7SB IMRSB IMWSB IPRSB IR0SB IR1SB IR2SB IR3SB IR4SB IR5SB IR6SB IR7SB ISYLP JAMSR JC0EB JC0OB JC1EB JC1OB JC2EB JC2OB JC3EB JC3OB JC4EB JC4OB JC5EB JC5OB JC6EB JC6OB JC7EB JC7OB JC8EB JC8OB JC9EB JC9OB JCAEB JCAOB JCBEB JCBOB JCCEB Description Invert interrupt GPIO 5 Invert interrupt GPIO 6 Invert interrupt GPIO 7 Invert MB read strobe Invert MB write strobe Invert MB PCIRSTn, forwarded Invert local reference 0 Invert local reference 1 Invert local reference 2 Invert local reference 3 Invert local reference 4 Invert local reference 5 Invert local reference 6 Invert local reference 7 Diag, internal control SYSERR Interrupt arbitration mode Interrupt from CLKERR 0 Interrupt pending CLKERR 0 Interrupt from CLKERR 1 Interrupt pending CLKERR 1 Interrupt from CLKERR 2 Interrupt pending CLKERR 2 Interrupt from CLKERR 3 Interrupt pending CLKERR 3 Interrupt from CLKERR 4 Interrupt pending CLKERR 4 Interrupt from CLKERR 5 Interrupt pending CLKERR 5 Interrupt from CLKERR 6 Interrupt pending CLKERR 6 Interrupt from CLKERR 7 Interrupt pending CLKERR 7 Interrupt from CLKERR 8 Interrupt pending CLKERR 8 Interrupt from CLKERR 9 Interrupt pending CLKERR 9 Interrupt from CLKERR A Interrupt pending CLKERR A Interrupt from CLKERR B Interrupt pending CLKERR B Interrupt from CLKERR C Type Select Select Select Select Select Select Select Select Select Select Select Select Select Select Load Select Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Register 0x00607 0x00607 0x00607 0x00781 0x00781 0x00781 0x0020C 0x0020C 0x0020C 0x0020C 0x0020C 0x0020C 0x0020C 0x0020C 0x00148 0x00610 0x0060E 0x0060C 0x0060E 0x0060C 0x0060E 0x0060C 0x0060E 0x0060C 0x0060E 0x0060C 0x0060E 0x0060C 0x0060E 0x0060C 0x0060E 0x0060C 0x0060F 0x0060D 0x0060F 0x0060D 0x0060F 0x0060D 0x0060F 0x0060D 0x0060F Bit Position 5 6 7 1 0 2 0 1 2 3 4 5 6 7 3:2 -- 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 133. Mnemonic Summary, Sorted by Name (continued) Mnemonic JCCOB JCDEB JCDOB JCEEB JCEOB JCFEB JCFOB JCOSR JCWSR JF0EB JF0OB JF1EB JF1OB JF2EB JF2OB JF3EB JF3OB JF4EB JF4OB JF5EB JF5OB JF6EB JF6OB JF7EB JF7OB JG0EB JG0OB JG1EB JG1OB JG2EB JG2OB JG3EB JG3OB JG4EB JG4OB JG5EB JG5OB JG6EB JG6OB JG7EB JG7OB Description Interrupt pending CLKERR C Interrupt from CLKERR D Interrupt pending CLKERR D Interrupt from CLKERR E Interrupt pending CLKERR E Interrupt from CLKERR F Interrupt pending CLKERR F Interrupt CLKERR output mode Interrupt CLKERR pulse width Interrupt from FGIO 0 Interrupt pending FGIO 0 Interrupt from FGIO 1 Interrupt pending FGIO 1 Interrupt from FGIO 2 Interrupt pending FGIO 2 Interrupt from FGIO 3 Interrupt pending FGIO 3 Interrupt from FGIO 4 Interrupt pending FGIO 4 Interrupt from FGIO 5 Interrupt pending FGIO 5 Interrupt from FGIO 6 Interrupt pending FGIO 6 Interrupt from FGIO 7 Interrupt pending FGIO 7 Interrupt from GPIO 0 Interrupt pending GPIO 0 Interrupt from GPIO 1 Interrupt pending GPIO 1 Interrupt from GPIO 2 Interrupt pending GPIO 2 Interrupt from GPIO 3 Interrupt pending GPIO 3 Interrupt from GPIO 4 Interrupt pending GPIO 4 Interrupt from GPIO 5 Interrupt pending GPIO 5 Interrupt from GPIO 6 Interrupt pending GPIO 6 Interrupt from GPIO 7 Interrupt pending GPIO 7 Type Output Enable Output Enable Output Enable Output Select Select Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Register 0x0060D 0x0060F 0x0060D 0x0060F 0x0060D 0x0060F 0x0060D 0x00613 0x00617 0x00601 0x00600 0x00601 0x00600 0x00601 0x00600 0x00601 0x00600 0x00601 0x00600 0x00601 0x00600 0x00601 0x00600 0x00601 0x00600 0x00605 0x00604 0x00605 0x00604 0x00605 0x00604 0x00605 0x00604 0x00605 0x00604 0x00605 0x00604 0x00605 0x00604 0x00605 0x00604 Bit Position 4 5 5 6 6 7 7 -- -- 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 133. Mnemonic Summary, Sorted by Name (continued) Mnemonic JISOR JS0EB JS0OB JS1EB JS1OB JS2EB JS2OB JS3EB JS3OB JS4EB JS4OB JS5EB JS5OB JS6EB JS6OB JS7EB JS7OB JS8EB JS8OB JS9EB JS9OB JSAEB JSAOB JSBEB JSBOB JSCEB JSCOB JSDEB JSDOB JSEEB JSEOB JSFEB JSFOB JSOSR JSPSR JSWSR JVHOB JVLOR LARSN LBRSN LC0SR Description Interrupt in-service Interrupt from SYSERR 0 Interrupt pending SYSERR 0 Interrupt from SYSERR 1 Interrupt pending SYSERR 1 Interrupt from SYSERR 2 Interrupt pending SYSERR 2 Interrupt from SYSERR 3 Interrupt pending SYSERR 3 Interrupt from SYSERR 4 Interrupt pending SYSERR 4 Interrupt from SYSERR 5 Interrupt pending SYSERR 5 Interrupt from SYSERR 6 Interrupt pending SYSERR 6 Interrupt from SYSERR 7 Interrupt pending SYSERR 7 Interrupt from SYSERR 8 Interrupt pending SYSERR 8 Interrupt from SYSERR 9 Interrupt pending SYSERR 9 Interrupt from SYSERR A Interrupt pending SYSERR A Interrupt from SYSERR B Interrupt pending SYSERR B Interrupt from SYSERR C Interrupt pending SYSERR C Interrupt from SYSERR D Interrupt pending SYSERR D Interrupt from SYSERR E Interrupt pending SYSERR E Interrupt from SYSERR F Interrupt pending SYSERR F Interrupt SYSERR output mode Interrupt SYSERR-to-PCI_INTA# Interrupt SYSERR pulse width Interrupt in-service VC ID high Interrupt in-service VC ID low Local group A rate Local group B rate Local clock 0 output Type Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Select Select Select Output Output Select Select Select Register 0x006FC 0x0060A 0x00608 0x0060A 0x00608 0x0060A 0x00608 0x0060A 0x00608 0x0060A 0x00608 0x0060A 0x00608 0x0060A 0x00608 0x0060A 0x00608 0x0060B 0x00609 0x0060B 0x00609 0x0060B 0x00609 0x0060B 0x00609 0x0060B 0x00609 0x0060B 0x00609 0x0060B 0x00609 0x0060B 0x00609 0x00612 0x00611 0x00616 0x006FF 0x006FE 0x00320 0x00320 0x00228 Bit Position -- 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 -- -- -- 0 -- L U --
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Agere Systems Inc.
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 133. Mnemonic Summary, Sorted by Name (continued) Mnemonic LC1SR LC2SR LC3SR LCKEB LCRSN LDBEB LDRSN LERSN LFRSN LGRSN LHRSN LRISR MBIEB MBPOB MBREB MBSOB MBTOB N1DSB N1DSN N1FEB N1ISN N1LOB N1LSR N1OEN N1SSB N1TOB N1WEB N1WSN N2DSB N2DSN N2FEB N2ISN N2LOB N2LSR N2OEN N2SSB N2TOB N2WEB N2WSN NQOOB NR1DR Description Local clock 1 output Local clock 2 output Local clock 3 output Local clocks Local group C rate Local data bus Local group D rate Local group E rate Local group F rate Local group G rate Local group H rate Local reference input Diag MB microprocessor access MB PCI error status Minibridge MB PCI queue status MB PCI timer status NR1 divider inversion NETREF1 divider input NETREF1 fallback trigger NETREF1 main input NETREF1 latched error NETREF1 local reference NETREF1 output NR1 selector inversion NETREF1 transient error NETREF1 watchdog NETREF1 watchdog NR2 divider inversion NETREF1 divider input NETREF2 fallback trigger NETREF1 main input NETREF2 latched error NETREF1 local reference NETREF1 output NR2 selector inversion NETREF2 transient error NETREF2 watchdog NETREF2 watchdog NOTIFY_QUEUE overflow error NETREF1 Type Select Select Select Enable Select Enable Select Select Select Select Select Select Enable Output Enable Output Output Select Select Enable Select Output Select Enable Select Output Enable Select Select Select Enable Select Output Select Enable Select Output Enable Select Output Divide Register 0x00229 0x0022A 0x0022B 0x00103 0x00321 0x00103 0x00321 0x00322 0x00322 0x00323 0x00323 0x00208 0x00146 0x00127 0x00103 0x00126 0x00127 0x00204 0x00210 0x0010B 0x00210 0x00123 0x00212 0x00221 0x00204 0x00121 0x0010F 0x0010D 0x00204 0x00214 0x0010B 0x00214 0x00123 0x00216 0x00221 0x00204 0x00121 0x0010F 0x0010D 0x00126 0x00211 Bit Position -- -- -- 1 L 0 U L U L U -- 4 2 6 2 5 1 U 3 L 3 -- L 0 3 3 L 3 U 4 L 4 -- U 2 4 4 U 0 --
Agere Systems Inc.
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 133. Mnemonic Summary, Sorted by Name (continued) Mnemonic NR2DR OLHLR OLLLR OOLER OOLOB P1ISR P1RSR P2RSR PAFSR PDTSB PMBEB PMEOB PMFOB PMIOB PMLOB PMOOB PMWOB PRBEB R0HLR R0SLR R0WLR R1HLR R1SLR R1WLR R2HLR R2SLR R2WLR R3HLR R3SLR R3WLR R4HLR R4SLR R4WLR R5HLR R5SLR R5WLR R6HLR R6SLR R6WLR R7HLR R7SLR Description NETREF2 Out-of-lock threshold, high Out-of-lock threshold, low Out-of-lock monitor Out-of-lock status APLL1 input APLL1 rate APLL2 rate Phase align frame Diag PCI discard timer PCI reset to minibridge PCI master stall error PCI master fatal error PCI master initial warning PCI master lock error PCI master overwrite PCI master stall warning PCI reset of back end MB_CS0 read cycle hold MB_CS0 read cycle setup MB_CS0 read cycle width MB_CS1 read cycle hold MB_CS1 read cycle setup MB_CS1 read cycle width MB_CS2 read cycle hold MB_CS2 read cycle setup MB_CS2 read cycle width MB_CS3 read cycle hold MB_CS3 read cycle setup MB_CS3 read cycle width MB_CS4 read cycle hold MB_CS4 read cycle setup MB_CS4 read cycle width MB_CS5 read cycle hold MB_CS5 read cycle setup MB_CS5 read cycle width MB_CS6 read cycle hold MB_CS6 read cycle setup MB_CS6 read cycle width MB_CS7 read cycle hold MB_CS7 read cycle setup Type Divide Load Load Enable Output Select Select Select Enable Select Enable Output Output Output Output Output Output Enable Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Register 0x00215 0x00119 0x00118 0x0011A 0x00125 0x00202 0x00203 0x00207 0x00107 0x00146 0x00101 0x00126 0x00126 0x00126 0x00126 0x00126 0x00126 0x00101 0x00702 0x00700 0x00701 0x00712 0x00710 0x00711 0x00722 0x00720 0x00721 0x00732 0x00730 0x00731 0x00742 0x00740 0x00741 0x00752 0x00750 0x00751 0x00762 0x00760 0x00761 0x00772 0x00770 Bit Position -- -- -- -- 6 -- -- -- -- 5 3 5 7 2 6 3 4 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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Agere Systems Inc.
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 133. Mnemonic Summary, Sorted by Name (continued) Mnemonic R7WLR S2FEB S2LOB S2TOB S2WEB SCFEB SCLOB SCLSB SCMLR SCMSB SCRSR SCTOB SCULP SCWEB SRBEB SRESR TCOSR VCEON VCMEB VCOOB VCPOB VCSOB VCSSR VCTOB VEROR VPPOB VSPOB W0HLR W0SLR W0WLR W1HLR W1SLR W1WLR W2HLR W2SLR W2WLR W3HLR W3SLR W3WLR W4HLR W4SLR Description MB_CS7 read cycle width /SCLKx2 fallback trigger /SCLKx2 latched error /SCLKx2 transient error /SCLKx2 watchdog SCLK fallback trigger SCLK latched error Diag state counter mode EN Diag state counter mode low Diag state counter carry SCLK/SCLKx2 rate SCLK transient error Diag state counter mode high SCLK watchdog Soft reset of back end Soft reset T clock output VC enable status Diag VC microprocessor access VC memory overflow warning VC memory PCI error VC memory PCI queue VC start command reg VC memory PCI timer Version ID register VC pause pending VC start pending MB_CS0 write cycle hold MB_CS0 write cycle setup MB_CS0 write cycle width MB_CS1 write cycle hold MB_CS1 write cycle setup MB_CS1 write cycle width MB_CS2 write cycle hold MB_CS2 write cycle setup MB_CS2 write cycle width MB_CS3 write cycle hold MB_CS3 write cycle setup MB_CS3 write cycle width MB_CS4 write cycle hold MB_CS4 write cycle setup Type Load Enable Output Output Enable Enable Output Select Load Select Select Output Load Enable Enable Select Select Output Enable Output Output Output Select Output Output Output Output Load Load Load Load Load Load Load Load Load Load Load Load Load Load Register 0x00771 0x0010A 0x00122 0x00120 0x0010E 0x0010A 0x00122 0x00145 0x00144 0x00145 0X00227 0x00120 0x00145 0x0010E 0x00101 0x00100 0x00226 0x0012D 0x00146 0x00126 0x00127 0x0012C 0x00104 0x00127 0x00128 0x0012D 0x0012D 0x00706 0x00704 0x00705 0x00716 0x00714 0x00715 0x00726 0x00724 0x00725 0x00736 0x00734 0x00735 0x00746 0x00744 Bit Position -- 7 7 7 7 6 6 3 -- 5 -- 6 2:0 6 0 -- -- L 3 1 1 1 -- 4 -- 5 4 -- -- -- -- -- -- -- -- -- -- -- -- -- --
Agere Systems Inc.
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 133. Mnemonic Summary, Sorted by Name (continued) Mnemonic W4WLR W5HLR W5SLR W5WLR W6HLR W6SLR W6WLR W7HLR W7SLR W7WLR XYSOB Description MB_CS4 write cycle width MB_CS5 write cycle hold MB_CS5 write cycle setup MB_CS5 write cycle width MB_CS6 write cycle hold MB_CS6 write cycle setup MB_CS6 write cycle width MB_CS7 write cycle hold MB_CS7 write cycle setup MB_CS7 write cycle width Active clock set Type Load Load Load Load Load Load Load Load Load Load Output Register 0x00745 0x00756 0x00754 0x00755 0x00766 0x00764 0x00765 0x00776 0x00774 0x00775 0x00124 Bit Position -- -- -- -- -- -- -- -- -- -- 3
Table 134. Mnemonic Summary, Sorted by Register Mnemonic SRESR SRBEB HRBEB PRBEB PMBEB LDBEB LCKEB HDBEB HCKEB GPIEB FGREB MBREB AIOEB VCSSR GSREB DMMSP CSASR FPASR PAFSR FBCSR FSMSN FTRSN CAFEB CBFEB CPFEB CMFEB Description Soft reset Soft reset of back end Hard reset of back end PCI reset of back end PCI reset to minibridge Local data bus Local clocks H1x0 data bus H1x0 clocks General-purpose I/O Frame group Minibridge All I/O (master) VC start command reg Global subrate Data memory mode Clock set access Frame phase alignment Phase align frame Fallback control Fallback secondary mode Fallback type C8A fallback trigger C8B fallback trigger /C16+ fallback trigger /C16- fallback trigger Type Select Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Select Enable Select Select Select Enable Select Select Select Enable Enable Enable Enable Register 0x00100 0x00101 0x00101 0x00101 0x00101 0x00103 0x00103 0x00103 0x00103 0x00103 0x00103 0x00103 0x00103 0x00104 0x00105 0x00105 0x00106 0x00107 0x00107 0x00108 0x00109 0x00109 0x0010A 0x0010A 0x0010A 0x0010A Bit Position -- 0 1 2 3 0 1 2 3 4 5 6 7 -- 7 6:0 -- -- -- -- L U 0 1 2 3
206
Agere Systems Inc.
Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 134. Mnemonic Summary, Sorted by Register (continued) Mnemonic C4FEB C2FEB SCFEB S2FEB FAFEB FBFEB FCFEB N1FEB N2FEB D1FEB D2FEB CAWSN CBWSN N1WSN N2WSN CAWEB CBWEB CPWEB CMWEB C4WEB C2WEB SCWEB S2WEB FAWEB FBWEB FCWEB N1WEB N2WEB D1WEB D2WEB FSWEB BA0LR BA1LR BA2LR BA3LR FSCSR FSEER FSSSR OLLLR OLHLR OOLER Description /C4 fallback trigger C2 fallback trigger SCLK fallback trigger /SCLKx2 fallback trigger /FRAMEA fallback trigger /FRAMEB fallback trigger /FR_COMP fallback trigger NETREF1 fallback trigger NETREF2 fallback trigger DPLL1 sync trigger DPLL2 sync trigger C8A watchdog C8B watchdog NETREF1 watchdog NETREF2 watchdog C8A watchdog C8B watchdog /C16+ watchdog /C16- watchdog /C4 watchdog C2 watchdog SCLK watchdog /SCLKx2 watchdog /FRAMEA watchdog /FRAMEB watchdog /FR_COMP watchdog NETREF1 watchdog NETREF2 watchdog DPLL1 sync watchdog DPLL2 sync watchdog Failsafe watchdog DT base address byte 0 DT base address byte 1 DT base address byte 2 DT base address byte 3 Failsafe return command Failsafe enable Failsafe sensitivity Out-of-lock threshold, low Out-of-lock threshold, high Out-of-lock monitor Type Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Select Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Load Load Load Load Select Enable Select Load Load Enable Register 0x0010A 0x0010A 0x0010A 0x0010A 0x0010B 0x0010B 0x0010B 0x0010B 0x0010B 0x0010B 0x0010B 0x0010C 0x0010C 0x0010D 0x0010D 0x0010E 0x0010E 0x0010E 0x0010E 0x0010E 0x0010E 0x0010E 0x0010E 0x0010F 0x0010F 0x0010F 0x0010F 0x0010F 0x0010F 0x0010F 0x0010F 0x00110 0x00111 0x00112 0x00113 0x00114 0x00115 0x00116 0x00118 0x00119 0x0011A Bit Position 4 5 6 7 0 1 2 3 4 5 6 L U L U 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 -- -- -- -- -- -- -- -- -- --
Agere Systems Inc.
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 134. Mnemonic Summary, Sorted by Register (continued) Mnemonic CATOB CBTOB CPTOB CMTOB C4TOB C2TOB SCTOB S2TOB FATOB FBTOB FCTOB N1TOB N2TOB D1TOB D2TOB FSTOB CALOB CBLOB CPLOB CMLOB C4LOB C2LOB SCLOB S2LOB FALOB FBLOB FCLOB N1LOB N2LOB D1LOB D2LOB FSLOB FFPOB CFPOB GOPOB XYSOB FBFOB FBSOP DPGOB CMROB OOLOB Description C8A transient error C8B transient error /C16+ transient error /C16- transient error C4 transient error C2 transient error SCLK transient error /SCLKx2 transient error /FRAMEA transient error /FRAMEB transient error /FR_COMP transient error NETREF1 transient error NETREF2 transient error DPLL1 sync transient error DPLL2 sync transient error Failsafe transient error C8A latched error C8B latched error /C16+ latched error /C16- latched error C4 latched error C2 latched error SCLK latched error /SCLKx2 latched error /FRAMEA latched error /FRAMEB latched error /FR_COMP latched error NETREF1 latched error NETREF2 latched error DPLL1 sync latched error DPLL2 sync latched error Failsafe latched error FORCE_FALLBACK pending CLEAR_FALLBACK pending Go clocks pending Active clock set Fallback enable status Fallback states Data memory active page Connection memory reset active Out-of-lock status Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Register 0x00120 0x00120 0x00120 0x00120 0x00120 0x00120 0x00120 0x00120 0x00121 0x00121 0x00121 0x00121 0x00121 0x00121 0x00121 0x00121 0x00122 0x00122 0x00122 0x00122 0x00122 0x00122 0x00122 0x00122 0x00123 0x00123 0x00123 0x00123 0x00123 0x00123 0x00123 0x00123 0x00124 0x00124 0x00124 0x00124 0x00124 0x00124 0x00125 0x00125 0x00125 Bit Position 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 7 6:4 0 1 6
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Agere Systems Inc.
Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 134. Mnemonic Summary, Sorted by Register (continued) Mnemonic A1LOB D2LOP D1LOP DMSOB NQOOB VCOOB MBSOB PMIOB PMOOB PMWOB PMEOB PMLOB PMFOB DMPOB VCPOB MBPOB DMTOB VCTOB MBTOB CFBOB CFSOB VEROR IDLOR IDHOR VCSOB VSPOB VPPOB VCEON FT0EB FT1EB FT2EB FT3EB FT4EB FT5EB FT6EB FT7EB FTPSR GT0EB GT1EB GT2EB GT3EB Description APLL1 lock indicator DPLL2 lock status DPLL1 lock status Data memory PCI queue status NOTIFY_QUEUE overflow error VC memory overflow warning MB PCI queue status PCI master initial warning PCI master overwrite PCI master stall warning PCI master stall error PCI master lock error PCI master fatal error Data memory PCI error status VC memory PCI error MB PCI error status Data memory PCI timer status VC memory PCI timer MB PCI timer status Fallback status Failsafe status Version ID register Device ID low Device ID high VC memory PCI queue VC start pending VC pause pending VC enable status FG0 test-point FG1 test-point FG2 test-point FG3 test-point FG4 test-point FG5 test-point FG6 test-point FG7 test-point FG test-point MUX GP0 test-point GP1 test-point GP2 test-point GP3 test-point Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Enable Enable Enable Enable Enable Enable Enable Enable Select Enable Enable Enable Enable Register 0x00125 0x00125 0x00125 0x00126 0x00126 0x00126 0x00126 0x00126 0x00126 0x00126 0x00126 0x00126 0x00126 0x00127 0x00127 0x00127 0x00127 0x00127 0x00127 0x00127 0x00127 0x00128 0x0012A 0x0012B 0x0012C 0x0012D 0x0012D 0x0012D 0x00140 0x00140 0x00140 0x00140 0x00140 0x00140 0x00140 0x00140 0x00141 0x00142 0x00142 0x00142 0x00142 Bit Position 7 3:2 5:4 0 0 1 2 2 3 4 5 6 7 0 1 2 3 4 5 6 7 -- -- -- 1 4 5 L 0 1 2 3 4 5 6 7 -- 0 1 2 3
Agere Systems Inc.
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 134. Mnemonic Summary, Sorted by Register (continued) Mnemonic GT4EB GT5EB GT6EB GT7EB GTPSR SCMLR SCLSB FRMSB SCMSB SCULP FB1SB FB2SB VCMEB MBIEB PDTSB EBOLR IEXLP ISYLP ICKLP ICDSP IASLR CFLLR CFHLN CFSEN CKMSR CKMDR P1ISR P1RSR N1SSB N1DSB N2SSB N2DSB ICMSB CKRDR P2RSR LRISR D1ISR D1RSR IR0SB IR1SB IR2SB Description GP4 test-point GP5 test-point GP6 test-point GP7 test-point GP test-point MUX Diagnostic, state counter mode low Diagnostic, state counter mode EN Diagnostic, /FR_COMP input Diagnostic, state counter carry Diagnostic, state counter mode high APLL1 feedback reset APLL2 feedback reset Diagnostic, VC microprocessor access Diagnostic, MB microprocessor access Diagnostic, PCI discard timer Diagnostic, external buffer retry Diagnostic, interrupt control EXTERR Diagnostic, interrupt control SYSERR Diagnostic, interrupt control CLKERR Diagnostic, interrupt control mode Diagnostic, SYSERR assertion Diagnostic sync-to-frame low Diagnostic sync-to-frame high Diagnostic sync-to-frame EN Clock main Clock main APLL1 input APLL1 rate NR1 selector inversion NR1 divider inversion NR2 selector inversion NR2 divider inversion Invert clock main Clock resource APLL2 rate Local reference input DPLL1 input DPLL1 rate Invert local reference 0 Invert local reference 1 Invert local reference 2 Type Enable Enable Enable Enable Select Load Select Select Select Load Select Select Enable Enable Select Load Load Load Load Select Load Load Load Enable Select Divide Select Select Select Select Select Select Select Divide Select Select Select Select Select Select Select Register 0x00142 0x00142 0x00142 0x00142 0x00143 0x00144 0x00145 0x00145 0x00145 0x00145 0x00146 0x00146 0x00146 0x00146 0x00146 0x00147 0x00148 0x00148 0x00148 0x00148 0x00149 0x0014A 0x0014B 0x0014B 0x00200 0x00201 0x00202 0x00203 0x00204 0x00204 0x00204 0x00204 0x00204 0x00205 0x00207 0x00208 0x0020A 0x0020B 0x0020C 0x0020C 0x0020C Bit Position 4 5 6 7 -- -- 3 4 5 2:0 1 2 3 4 5 -- 1:0 3:2 5:4 7:6 -- -- L U -- -- -- -- 0 1 2 3 4 -- -- -- -- -- 0 1 2
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Agere Systems Inc.
Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 134. Mnemonic Summary, Sorted by Register (continued) Mnemonic IR3SB IR4SB IR5SB IR6SB IR7SB D2ISR D2RSR N1ISN N1DSN NR1DR N1LSR N2ISN N2DSN NR2DR N2LSR CCOEN ABOEN N1OEN N2OEN FRWSR ACRSN BCRSN CCSEN FRSEN TCOSR SCRSR LC0SR LC1SR LC2SR LC3SR HARSN HBRSN HCRSN HDRSN HERSN HFRSN HGRSN HHRSN LARSN LBRSN LCRSN Description Invert local reference 3 Invert local reference 4 Invert local reference 5 Invert local reference 6 Invert local reference 7 DPLL2 input DPLL2 rate NETREF1 main input NETREF1 divider input NETREF1 NETREF1 local reference NETREF1 main input NETREF1 divider input NETREF2 NETREF1 local reference C clocks output A and B clocks output NETREF1 output NETREF1 output /FR_COMP width A clocks rate B clocks rate C clocks separate /FR_COMP separate T clock output SCLK/SCLKx2 rate Local clock 0 output Local clock 1 output Local clock 2 output Local clock 3 output H1x0 group A rate H1x0 group B rate H1x0 group C rate H1x0 group D rate H1x0 group E rate H1x0 group F rate H1x0 group G rate H1x0 group H rate Local group A rate Local group B rate Local group C rate Type Select Select Select Select Select Select Select Select Select Divide Select Select Select Divide Select Enable Enable Enable Enable Select Select Select Enable Enable Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Register 0x0020C 0x0020C 0x0020C 0x0020C 0x0020C 0x0020E 0x0020F 0x00210 0x00210 0x00211 0x00212 0x00214 0x00214 0x00215 0x00216 0x00220 0x00220 0x00221 0x00221 0x00222 0x00223 0x00223 0x00224 0x00224 0x00226 0x00227 0x00228 0x00229 0x0022A 0x0022B 0x00300 0x00300 0x00301 0x00301 0x00302 0x00302 0x00303 0x00303 0x00320 0x00320 0x00321 Bit Position 3 4 5 6 7 -- -- L U -- -- L U -- -- L U L U -- L U L U -- -- -- -- -- -- L U L U L U L U L U L
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Data Sheet May 2001
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 134. Mnemonic Summary, Sorted by Register (continued) Mnemonic LDRSN LERSN LFRSN LGRSN LHRSN F0LLR F0ULR F0ISB F0WSP F0RSR F1LLR F1ULR F1ISB F1WSP F1RSR F2LLR F2ULR F2ISB F2WSP F2RSR F3LLR F3ULR F3ISB F3WSP F3RSR F4LLR F4ULR F4ISB F4WSP F4RSR F5LLR F5ULR F5ISB F5WSP F5RSR F6LLR F6ULR F6ISB F6WSP F6RSR F7LLR Description Local group D rate Local group E rate Local group F rate Local group G rate Local group H rate Frame 0 lower start time Frame 0 upper start time Frame 0 pulse inversion Frame 0 pulse width Frame 0 pulse width rate Frame 1 lower start time Frame 1 upper start time Frame 1 pulse inversion Frame 1 pulse width Frame 1 pulse width rate Frame 2 lower start time Frame 2 upper start time Frame 2 pulse inversion Frame 2 pulse width Frame 2 pulse width rate Frame 3 lower start time Frame 3 upper start time Frame 3 pulse inversion Frame 3 pulse width Frame 3 pulse width rate Frame 4 lower start time Frame 4 upper start time Frame 4 pulse inversion Frame 4 pulse width Frame 4 pulse width rate Frame 5 lower start time Frame 5 upper start time Frame 5 pulse inversion Frame 5 pulse width Frame 5 pulse width rate Frame 6 lower start time Frame 6 upper start time Frame 6 pulse inversion Frame 6 pulse width Frame 6 pulse width rate Frame 7 lower start time Type Select Select Select Select Select Load Load Enable Select Select Load Load Enable Select Select Load Load Enable Select Select Load Load Enable Select Select Load Load Enable Select Select Load Load Enable Select Select Load Load Enable Select Select Load Register 0x00321 0x00322 0x00322 0x00323 0x00323 0x00400 0x00401 0x00402 0x00402 0x00403 0x00410 0x00411 0x00412 0x00412 0x00413 0x00420 0x00421 0x00422 0x00422 0x00423 0x00430 0x00431 0x00432 0x00432 0x00433 0x00440 0x00441 0x00442 0x00442 0x00443 0x00450 0x00451 0x00452 0x00452 0x00453 0x00460 0x00461 0x00462 0x00462 0x00463 0x00470 Bit Position U L U L U -- -- 7 6:0 -- -- -- 7 6:0 -- -- -- 7 6:0 -- -- -- 7 6:0 -- -- -- 7 6:0 -- -- -- 7 6:0 -- -- -- 7 6:0 -- --
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Agere Systems Inc.
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 134. Mnemonic Summary, Sorted by Register (continued) Mnemonic F7ULR F7ISB F7WSP F7RSR FCLLR FCULR F7MSR FCISB F7WSN F7SSP F0IOB F1IOB F2IOB F3IOB F4IOB F5IOB F6IOB F7IOB F0MEB F1MEB F2MEB F3MEB F4MEB F5MEB F6MEB F7MEB F0DSB F1DSB F2DSB F3DSB F4DSB F5DSB F6DSB F7DSB G0IOB G1IOB G2IOB G3IOB G4IOB G5IOB G6IOB Description Frame 7 upper start time Frame 7 pulse inversion Frame 7 pulse width Frame 7 pulse width rate Frame group 7 lower count Frame group 7 upper count Frame 7 mode FG7 timer invert output FG7 timer pulse width FG7 timer pulse shape FGIO 0 data FGIO 1 data FGIO 2 data FGIO 3 data FGIO 4 data FGIO 5 data FGIO 6 data FGIO 7 data FGIO 0 read mask FGIO 1 read mask FGIO 2 read mask FGIO 3 read mask FGIO 4 read mask FGIO 5 read mask FGIO 6 read mask FGIO 7 read mask FGIO 0 R/W direction FGIO 1 R/W direction FGIO 2 R/W direction FGIO 3 R/W direction FGIO 4 R/W direction FGIO 5 R/W direction FGIO 6 R/W direction FGIO 7 R/W direction GPIO 0 data GPIO 1 data GPIO 2 data GPIO 3 data GPIO 4 data GPIO 5 data GPIO 6 data Type Load Enable Select Select Load Load Select Select Select Select Load Load Load Load Load Load Load Load Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Select Select Select Select Select Load Load Load Load Load Load Load Register 0x00471 0x00472 0x00472 0x00473 0x00474 0x00475 0x00476 0x00477 0x00477 0x00477 0x00480 0x00480 0x00480 0x00480 0x00480 0x00480 0x00480 0x00480 0x00481 0x00481 0x00481 0x00481 0x00481 0x00481 0x00481 0x00481 0x00482 0x00482 0x00482 0x00482 0x00482 0x00482 0x00482 0x00482 0x00500 0x00500 0x00500 0x00500 0x00500 0x00500 0x00500 Bit Position -- 7 6:0 -- -- -- -- 7 L -- 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 134. Mnemonic Summary, Sorted by Register (continued) Mnemonic G7IOB G0MEB G1MEB G2MEB G3MEB G4MEB G5MEB G6MEB G7MEB G0DSB G1DSB G2DSB G3DSB G4DSB G5DSB G6DSB G7DSB G0OEB G1OEB G2OEB JF0OB JF1OB JF2OB JF3OB JF4OB JF5OB JF6OB JF7OB JF0EB JF1EB JF2EB JF3EB JF4EB JF5EB JF6EB JF7EB IF0SB IF1SB IF2SB IF3SB IF4SB Description GPIO 7 data PIO 0 read mask GPIO 1 read mask GPIO 2 read mask GPIO 3 read mask GPIO 4 read mask GPIO 5 read mask GPIO 6 read mask GPIO 7 read mask GPIO 0 R/W direction GPIO 1 R/W direction GPIO 2 R/W direction GPIO 3 R/W direction GPIO 4 R/W direction GPIO 5 R/W direction GPIO 6 R/W direction GPIO 7 R/W direction GPIO 0 override GPIO 0 override GPIO 2 override Interrupt pending FGIO 0 Interrupt pending FGIO 1 Interrupt pending FGIO 2 Interrupt pending FGIO 3 Interrupt pending FGIO 4 Interrupt pending FGIO 5 Interrupt pending FGIO 6 Interrupt pending FGIO 7 Interrupt from FGIO 0 Interrupt from FGIO 1 Interrupt from FGIO 2 Interrupt from FGIO 3 Interrupt from FGIO 4 Interrupt from FGIO 5 Interrupt from FGIO 6 Interrupt from FGIO 7 Invert interrupt FGIO 0 Invert interrupt FGIO 1 Invert interrupt FGIO 2 Invert interrupt FGIO 3 Invert interrupt FGIO 4 Type Load Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Select Select Select Select Select Enable Enable Enable Output Output Output Output Output Output Output Output Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Select Select Register 0x00500 0x00501 0x00501 0x00501 0x00501 0x00501 0x00501 0x00501 0x00501 0x00502 0x00502 0x00502 0x00502 0x00502 0x00502 0x00502 0x00502 0x00503 0x00503 0x00503 0x00600 0x00600 0x00600 0x00600 0x00600 0x00600 0x00600 0x00600 0x00601 0x00601 0x00601 0x00601 0x00601 0x00601 0x00601 0x00601 0x00603 0x00603 0x00603 0x00603 0x00603 Bit Position 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4
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Agere Systems Inc.
Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 134. Mnemonic Summary, Sorted by Register (continued) Mnemonic IF5SB IF6SB IF7SB JG0OB JG1OB JG2OB JG3OB JG4OB JG5OB JG6OB JG7OB JG0EB JG1EB JG2EB JG3EB JG4EB JG5EB JG6EB JG7EB IG0SB IG1SB IG2SB IG3SB IG4SB IG5SB IG6SB IG7SB JS0OB JS1OB JS2OB JS3OB JS4OB JS5OB JS6OB JS7OB JS8OB JS9OB JSAOB JSBOB JSCOB JSDOB Description Invert interrupt FGIO 5 Invert interrupt FGIO 6 Invert interrupt FGIO 7 Interrupt pending GPIO 0 Interrupt pending GPIO 1 Interrupt pending GPIO 2 Interrupt pending GPIO 3 Interrupt pending GPIO 4 Interrupt pending GPIO 5 Interrupt pending GPIO 6 Interrupt pending GPIO 7 Interrupt from GPIO 0 Interrupt from GPIO 1 Interrupt from GPIO 2 Interrupt from GPIO 3 Interrupt from GPIO 4 Interrupt from GPIO 5 Interrupt from GPIO 6 Interrupt from GPIO 7 Invert interrupt GPIO 0 Invert interrupt GPIO 1 Invert interrupt GPIO 2 Invert interrupt GPIO 3 Invert interrupt GPIO 4 Invert interrupt GPIO 5 Invert interrupt GPIO 6 Invert interrupt GPIO 7 Interrupt pending SYSERR 0 Interrupt pending SYSERR 1 Interrupt pending SYSERR 2 Interrupt pending SYSERR 3 Interrupt pending SYSERR 4 Interrupt pending SYSERR 5 Interrupt pending SYSERR 6 Interrupt pending SYSERR 7 Interrupt pending SYSERR 8 Interrupt pending SYSERR 9 Interrupt pending SYSERR A Interrupt pending SYSERR B Interrupt pending SYSERR C Interrupt pending SYSERR D Type Select Select Select Output Output Output Output Output Output Output Output Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Select Select Select Select Select Output Output Output Output Output Output Output Output Output Output Output Output Output Output Register 0x00603 0x00603 0x00603 0x00604 0x00604 0x00604 0x00604 0x00604 0x00604 0x00604 0x00604 0x00605 0x00605 0x00605 0x00605 0x00605 0x00605 0x00605 0x00605 0x00607 0x00607 0x00607 0x00607 0x00607 0x00607 0x00607 0x00607 0x00608 0x00608 0x00608 0x00608 0x00608 0x00608 0x00608 0x00608 0x00609 0x00609 0x00609 0x00609 0x00609 0x00609 Bit Position 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 134. Mnemonic Summary, Sorted by Register (continued) Mnemonic JSEOB JSFOB JS0EB JS1EB JS2EB JS3EB JS4EB JS5EB JS6EB JS7EB JS8EB JS9EB JSAEB JSBEB JSCEB JSDEB JSEEB JSFEB JC0OB JC1OB JC2OB JC3OB JC4OB JC5OB JC6OB JC7OB JC8OB JC9OB JCAOB JCBOB JCCOB JCDOB JCEOB JCFOB JC0EB JC1EB JC2EB JC3EB JC4EB JC5EB JC6EB Description Interrupt pending SYSERR E Interrupt pending SYSERR F Interrupt from SYSERR 0 Interrupt from SYSERR 1 Interrupt from SYSERR 2 Interrupt from SYSERR 3 Interrupt from SYSERR 4 Interrupt from SYSERR 5 Interrupt from SYSERR 6 Interrupt from SYSERR 7 Interrupt from SYSERR 8 Interrupt from SYSERR 9 Interrupt from SYSERR A Interrupt from SYSERR B Interrupt from SYSERR C Interrupt from SYSERR D Interrupt from SYSERR E Interrupt from SYSERR F Interrupt pending CLKERR 0 Interrupt pending CLKERR 1 Interrupt pending CLKERR 2 Interrupt pending CLKERR 3 Interrupt pending CLKERR 4 Interrupt pending CLKERR 5 Interrupt pending CLKERR 6 Interrupt pending CLKERR 7 Interrupt pending CLKERR 8 Interrupt pending CLKERR 9 Interrupt pending CLKERR A Interrupt pending CLKERR B Interrupt pending CLKERR C Interrupt pending CLKERR D Interrupt pending CLKERR E Interrupt pending CLKERR F Interrupt from CLKERR 0 Interrupt from CLKERR 1 Interrupt from CLKERR 2 Interrupt from CLKERR 3 Interrupt from CLKERR 4 Interrupt from CLKERR 5 Interrupt from CLKERR 6 Type Output Output Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Enable Enable Enable Enable Enable Enable Enable Register 0x00609 0x00609 0x0060A 0x0060A 0x0060A 0x0060A 0x0060A 0x0060A 0x0060A 0x0060A 0x0060B 0x0060B 0x0060B 0x0060B 0x0060B 0x0060B 0x0060B 0x0060B 0x0060C 0x0060C 0x0060C 0x0060C 0x0060C 0x0060C 0x0060C 0x0060C 0x0060D 0x0060D 0x0060D 0x0060D 0x0060D 0x0060D 0x0060D 0x0060D 0x0060E 0x0060E 0x0060E 0x0060E 0x0060E 0x0060E 0x0060E Bit Position 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6
216
Agere Systems Inc.
Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 134. Mnemonic Summary, Sorted by Register (continued) Mnemonic JC7EB JC8EB JC9EB JCAEB JCBEB JCCEB JCDEB JCEEB JCFEB JAMSR JSPSR JSOSR JCOSR JSWSR JCWSR JISOR JVLOR JVHOB R0SLR R0WLR R0HLR A0SLR W0SLR W0WLR W0HLR R1SLR R1WLR R1HLR A1SLR W1SLR W1WLR W1HLR A1HLR R2SLR R2WLR R2HLR A2SLR W2SLR W2WLR W2HLR A2HLR Description Interrupt from CLKERR 7 Interrupt from CLKERR 8 Interrupt from CLKERR 9 Interrupt from CLKERR A Interrupt from CLKERR B Interrupt from CLKERR C Interrupt from CLKERR D Interrupt from CLKERR E Interrupt from CLKERR F Interrupt arbitration mode Interrupt SYSERR-to-PCI_INTA Interrupt SYSERR output mode Interrupt CLKERR output mode Interrupt SYSERR pulse width Interrupt CLKERR pulse width Interrupt in-service Interrupt in-service VC ID low Interrupt in-service VC ID high MB_CS0 read cycle setup MB_CS0 read cycle width MB_CS0 read cycle hold MB_CS0 address setup MB_CS0 write cycle setup MB_CS0 write cycle width MB_CS0 write cycle hold MB_CS1 read cycle setup MB_CS1 read cycle width MB_CS1 read cycle hold MB_CS1 address setup MB_CS1 write cycle setup MB_CS1 write cycle width MB_CS1 write cycle hold MB_CS1 address hold MB_CS2 read cycle setup MB_CS2 read cycle width MB_CS2 read cycle hold MB_CS2 address setup MB_CS2 write cycle setup MB_CS2 write cycle width MB_CS2 write cycle hold MB_CS2 address hold Type Enable Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Select Select Select Output Output Output Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Register 0x0060E 0x0060F 0x0060F 0x0060F 0x0060F 0x0060F 0x0060F 0x0060F 0x0060F 0x00610 0x00611 0x00612 0x00613 0x00616 0x00617 0x006FC 0x006FE 0x006FF 0x00700 0x00701 0x00702 0x00703 0x00704 0x00705 0x00706 0x00710 0x00711 0x00712 0x00713 0x00714 0x00715 0x00716 0x00717 0x00720 0x00721 0x00722 0x00723 0x00724 0x00725 0x00726 0x00727 Bit Position 7 0 1 2 3 4 5 6 7 -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Agere Systems Inc.
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Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Data Sheet May 2001
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 134. Mnemonic Summary, Sorted by Register (continued) Mnemonic R3SLR R3WLR R3HLR A3SLR W3SLR W3WLR W3HLR A3HLR R4SLR R4WLR R4HLR A4SLR W4SLR W4WLR W4HLR A4HLR R5SLR R5WLR R5HLR A5SLR W5SLR W5WLR W5HLR A5HLR R6SLR R6WLR R6HLR A6SLR W6SLR W6WLR W6HLR A6HLR R7SLR R7WLR R7HLR A7SLR W7SLR W7WLR W7HLR A7HLR IC0SB Description MB_CS3 read cycle setup MB_CS3 read cycle width MB_CS3 read cycle hold MB_CS3 address setup MB_CS3 write cycle setup MB_CS3 write cycle width MB_CS3 write cycle hold MB_CS3 address hold MB_CS4 read cycle setup MB_CS4 read cycle width MB_CS4 read cycle hold MB_CS4 address setup MB_CS4 write cycle setup MB_CS4 write cycle width MB_CS4 write cycle hold MB_CS4 address hold MB_CS5 read cycle setup MB_CS5 read cycle width MB_CS5 read cycle hold MB_CS5 address setup MB_CS5 write cycle setup MB_CS5 write cycle width MB_CS5 write cycle hold MB_CS5 address hold MB_CS6 read cycle setup MB_CS6 read cycle width MB_CS6 read cycle hold MB_CS6 address setup MB_CS6 write cycle setup MB_CS6 write cycle width MB_CS6 write cycle hold MB_CS6 address hold MB_CS7 read cycle setup MB_CS7 read cycle width MB_CS7 read cycle hold MB_CS7 address setup MB_CS7 write cycle setup MB_CS7 write cycle width MB_CS7 write cycle hold MB_CS7 address hold Invert MB CS0 strobe Type Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Select Register 0x00730 0x00731 0x00732 0x00733 0x00734 0x00735 0x00736 0x00737 0x00740 0x00741 0x00742 0x00743 0x00744 0x00745 0x00746 0x00747 0x00750 0x00751 0x00752 0x00753 0x00754 0x00755 0x00756 0x00757 0x00760 0x00761 0x00762 0x00763 0x00764 0x00765 0x00766 0x00767 0x00770 0x00771 0x00772 0x00773 0x00774 0x00775 0x00776 0x00777 0x00780 Bit Position -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0
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Agere Systems Inc.
Data Sheet May 2001
Ambassador T8110 PCI-Based H.100/H.110 Switch and Packet Payload Engine
Appendix B. Register Bit Field Mnemonic Summary (continued)
Table 134. Mnemonic Summary, Sorted by Register (continued) Mnemonic IC1SB IC2SB IC3SB IC4SB IC5SB IC6SB IC7SB IMWSB IMRSB IPRSB Description Invert MB CS1 strobe Invert MB CS2 strobe Invert MB CS3 strobe Invert MB CS4 strobe Invert MB CS5 strobe Invert MB CS6 strobe Invert MB CS7 strobe Invert MB write strobe Invert MB read strobe Invert MB PCIRST, forwarded Type Select Select Select Select Select Select Select Select Select Select Register 0x00780 0x00780 0x00780 0x00780 0x00780 0x00780 0x00780 0x00781 0x00781 0x00781 Bit Position 1 2 3 4 5 6 7 0 1 2
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For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Ambassador is a registered trademark of Agere Systems Inc.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved
May 2001 DS00-434CTI (Replaces DS00-012CTI, AY00-030CTI, and AY01-009CTI; must accompany AY01-021CTI)

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